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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX8 DSP core8 9maintainers:10 - Daniel Baluta <daniel.baluta@nxp.com>11 - Shengjiu Wang <shengjiu.wang@nxp.com>12 13description: |14 Some boards from i.MX8 family contain a DSP core used for15 advanced pre- and post- audio processing.16 17properties:18 compatible:19 enum:20 - fsl,imx8qxp-dsp21 - fsl,imx8qm-dsp22 - fsl,imx8mp-dsp23 - fsl,imx8ulp-dsp24 - fsl,imx8qxp-hifi425 - fsl,imx8qm-hifi426 - fsl,imx8mp-hifi427 - fsl,imx8ulp-hifi428 29 reg:30 maxItems: 131 32 clocks:33 items:34 - description: ipg clock35 - description: ocram clock36 - description: core clock37 - description: debug interface clock38 - description: message unit clock39 minItems: 340 41 clock-names:42 items:43 - const: ipg44 - const: ocram45 - const: core46 - const: debug47 - const: mu48 minItems: 349 50 power-domains:51 description:52 List of phandle and PM domain specifier as documented in53 Documentation/devicetree/bindings/power/power_domain.txt54 minItems: 155 maxItems: 456 57 mboxes:58 description:59 List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB60 or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB61 (see mailbox/fsl,mu.txt)62 minItems: 363 maxItems: 464 65 mbox-names:66 minItems: 367 maxItems: 468 69 memory-region:70 description:71 phandle to a node describing reserved memory (System RAM memory)72 used by DSP (see bindings/reserved-memory/reserved-memory.txt)73 minItems: 174 maxItems: 475 76 firmware-name:77 description: |78 Default name of the firmware to load to the remote processor.79 80 fsl,dsp-ctrl:81 $ref: /schemas/types.yaml#/definitions/phandle82 description:83 Phandle to syscon block which provide access for processor enablement84 85required:86 - compatible87 - reg88 - clocks89 - clock-names90 - power-domains91 - mboxes92 - mbox-names93 - memory-region94 95allOf:96 - if:97 properties:98 compatible:99 contains:100 enum:101 - fsl,imx8qxp-dsp102 - fsl,imx8qm-dsp103 - fsl,imx8qxp-hifi4104 - fsl,imx8qm-hifi4105 then:106 properties:107 power-domains:108 minItems: 4109 else:110 properties:111 power-domains:112 maxItems: 1113 114 - if:115 properties:116 compatible:117 contains:118 enum:119 - fsl,imx8qxp-hifi4120 - fsl,imx8qm-hifi4121 - fsl,imx8mp-hifi4122 - fsl,imx8ulp-hifi4123 then:124 properties:125 memory-region:126 minItems: 4127 mboxes:128 maxItems: 3129 mbox-names:130 items:131 - const: tx132 - const: rx133 - const: rxdb134 else:135 properties:136 memory-region:137 maxItems: 1138 mboxes:139 minItems: 4140 mbox-names:141 items:142 - const: txdb0143 - const: txdb1144 - const: rxdb0145 - const: rxdb1146 147additionalProperties: false148 149examples:150 - |151 #include <dt-bindings/firmware/imx/rsrc.h>152 #include <dt-bindings/clock/imx8-clock.h>153 dsp@596e8000 {154 compatible = "fsl,imx8qxp-dsp";155 reg = <0x596e8000 0x88000>;156 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,157 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,158 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;159 clock-names = "ipg", "ocram", "core";160 power-domains = <&pd IMX_SC_R_MU_13A>,161 <&pd IMX_SC_R_MU_13B>,162 <&pd IMX_SC_R_DSP>,163 <&pd IMX_SC_R_DSP_RAM>;164 mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";165 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;166 memory-region = <&dsp_reserved>;167 };168 - |169 #include <dt-bindings/clock/imx8mp-clock.h>170 dsp_reserved: dsp@92400000 {171 reg = <0x92400000 0x1000000>;172 no-map;173 };174 dsp_vdev0vring0: vdev0vring0@942f0000 {175 reg = <0x942f0000 0x8000>;176 no-map;177 };178 dsp_vdev0vring1: vdev0vring1@942f8000 {179 reg = <0x942f8000 0x8000>;180 no-map;181 };182 dsp_vdev0buffer: vdev0buffer@94300000 {183 compatible = "shared-dma-pool";184 reg = <0x94300000 0x100000>;185 no-map;186 };187 188 dsp: dsp@3b6e8000 {189 compatible = "fsl,imx8mp-hifi4";190 reg = <0x3b6e8000 0x88000>;191 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,192 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,193 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,194 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;195 clock-names = "ipg", "ocram", "core", "debug";196 firmware-name = "imx/dsp/hifi4.bin";197 power-domains = <&audiomix_pd>;198 mbox-names = "tx", "rx", "rxdb";199 mboxes = <&mu2 0 0>,200 <&mu2 1 0>,201 <&mu2 3 0>;202 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,203 <&dsp_vdev0vring1>, <&dsp_reserved>;204 fsl,dsp-ctrl = <&audio_blk_ctrl>;205 };206