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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek mt8186 DSP core8 9maintainers:10 - Tinghan Shen <tinghan.shen@mediatek.com>11 12description: |13 MediaTek mt8186 SoC contains a DSP core used for14 advanced pre- and post- audio processing.15 16properties:17 compatible:18 enum:19 - mediatek,mt8186-dsp20 - mediatek,mt8188-dsp21 22 reg:23 items:24 - description: Address and size of the DSP config registers25 - description: Address and size of the DSP SRAM26 - description: Address and size of the DSP secure registers27 - description: Address and size of the DSP bus registers28 29 reg-names:30 items:31 - const: cfg32 - const: sram33 - const: sec34 - const: bus35 36 clocks:37 items:38 - description: mux for audio dsp clock39 - description: mux for audio dsp local bus40 41 clock-names:42 items:43 - const: audiodsp44 - const: adsp_bus45 46 power-domains:47 maxItems: 148 49 mboxes:50 items:51 - description: mailbox for receiving audio DSP requests.52 - description: mailbox for transmitting requests to audio DSP.53 54 mbox-names:55 items:56 - const: rx57 - const: tx58 59 memory-region:60 items:61 - description: dma buffer between host and DSP.62 - description: DSP system memory.63 64required:65 - compatible66 - reg67 - reg-names68 - clocks69 - clock-names70 - power-domains71 - mbox-names72 - mboxes73 74additionalProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/mt8186-clk.h>79 dsp@10680000 {80 compatible = "mediatek,mt8186-dsp";81 reg = <0x10680000 0x2000>,82 <0x10800000 0x100000>,83 <0x1068b000 0x100>,84 <0x1068f000 0x1000>;85 reg-names = "cfg", "sram", "sec", "bus";86 clocks = <&topckgen CLK_TOP_AUDIODSP>,87 <&topckgen CLK_TOP_ADSP_BUS>;88 clock-names = "audiodsp",89 "adsp_bus";90 power-domains = <&spm 6>;91 mbox-names = "rx", "tx";92 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;93 };94