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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: FPGA Region8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12description: |13 CONTENTS14 - Introduction15 - Terminology16 - Sequence17 - FPGA Region18 - Supported Use Models19 - Constraints20 21 22 Introduction23 ============24 25 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in26 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree27 control.28 29 The documentation hits some of the high points of FPGA usage and30 attempts to include terminology used by both major FPGA manufacturers. This31 document isn't a replacement for any manufacturers specifications for FPGA32 usage.33 34 35 Terminology36 ===========37 38 Full Reconfiguration39 * The entire FPGA is programmed.40 41 Partial Reconfiguration (PR)42 * A section of an FPGA is reprogrammed while the rest of the FPGA is not43 affected.44 * Not all FPGA's support PR.45 46 Partial Reconfiguration Region (PRR)47 * Also called a "reconfigurable partition"48 * A PRR is a specific section of an FPGA reserved for reconfiguration.49 * A base (or static) FPGA image may create a set of PRR's that later may50 be independently reprogrammed many times.51 * The size and specific location of each PRR is fixed.52 * The connections at the edge of each PRR are fixed. The image that is loaded53 into a PRR must fit and must use a subset of the region's connections.54 * The busses within the FPGA are split such that each region gets its own55 branch that may be gated independently.56 57 Persona58 * Also called a "partial bit stream"59 * An FPGA image that is designed to be loaded into a PRR. There may be60 any number of personas designed to fit into a PRR, but only one at a time61 may be loaded.62 * A persona may create more regions.63 64 FPGA Bridge65 * FPGA Bridges gate bus signals between a host and FPGA.66 * FPGA Bridges should be disabled while the FPGA is being programmed to67 prevent spurious signals on the cpu bus and to the soft logic.68 * FPGA bridges may be actual hardware or soft logic on an FPGA.69 * During Full Reconfiguration, hardware bridges between the host and FPGA70 will be disabled.71 * During Partial Reconfiguration of a specific region, that region's bridge72 will be used to gate the busses. Traffic to other regions is not affected.73 * In some implementations, the FPGA Manager transparently handles gating the74 buses, eliminating the need to show the hardware FPGA bridges in the75 device tree.76 * An FPGA image may create a set of reprogrammable regions, each having its77 own bridge and its own split of the busses in the FPGA.78 79 FPGA Manager80 * An FPGA Manager is a hardware block that programs an FPGA under the control81 of a host processor.82 83 Base Image84 * Also called the "static image"85 * An FPGA image that is designed to do full reconfiguration of the FPGA.86 * A base image may set up a set of partial reconfiguration regions that may87 later be reprogrammed.88 89 ---------------- ----------------------------------90 | Host CPU | | FPGA |91 | | | |92 | ----| | ----------- -------- |93 | | H | | |==>| Bridge0 |<==>| PRR0 | |94 | | W | | | ----------- -------- |95 | | | | | |96 | | B |<=====>|<==| ----------- -------- |97 | | R | | |==>| Bridge1 |<==>| PRR1 | |98 | | I | | | ----------- -------- |99 | | D | | | |100 | | G | | | ----------- -------- |101 | | E | | |==>| Bridge2 |<==>| PRR2 | |102 | ----| | ----------- -------- |103 | | | |104 ---------------- ----------------------------------105 106 Figure 1: An FPGA set up with a base image that created three regions. Each107 region (PRR0-2) gets its own split of the busses that is independently gated by108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be109 reprogrammed independently while the rest of the system continues to function.110 111 112 Sequence113 ========114 115 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will116 do the following:117 118 1. Disable appropriate FPGA bridges.119 2. Program the FPGA using the FPGA manager.120 3. Enable the FPGA bridges.121 4. The Device Tree overlay is accepted into the live tree.122 5. Child devices are populated.123 124 When the overlay is removed, the child nodes will be removed and the FPGA Region125 will disable the bridges.126 127 128 FPGA Region129 ===========130 131 FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA132 Region brings together the elements needed to program on a running system and133 add the child devices:134 135 * FPGA Manager136 * FPGA Bridges137 * image-specific information needed to the programming.138 * child nodes139 140 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an141 FPGA while an operating system is running.142 143 An FPGA Region that exists in the live Device Tree reflects the current state.144 If the live tree shows a "firmware-name" property or child nodes under an FPGA145 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region146 and adds the "firmware-name" property is taken as a request to reprogram the147 FPGA. After reprogramming is successful, the overlay is accepted into the live148 tree.149 150 The base FPGA Region in the device tree represents the FPGA and supports full151 reconfiguration. It must include a phandle to an FPGA Manager. The base152 FPGA region will be the child of one of the hardware bridges (the bridge that153 allows register access) between the cpu and the FPGA. If there are more than154 one bridge to control during FPGA programming, the region will also contain a155 list of phandles to the additional hardware FPGA Bridges.156 157 For partial reconfiguration (PR), each PR region will have an FPGA Region.158 These FPGA regions are children of FPGA bridges which are then children of the159 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows160 this.161 162 If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA163 Manager specified by its ancestor FPGA Region. This supports both the case164 where the same FPGA Manager is used for all of an FPGA as well the case where165 a different FPGA Manager is used for each region.166 167 FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents168 shutting down bridges that are upstream from the other active regions while one169 region is getting reconfigured (see Figure 1 above). During PR, the FPGA's170 hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges171 within the static image of the FPGA.172 173 174 Supported Use Models175 ====================176 177 In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and178 a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some179 uses are specific to an FPGA device.180 181 * No FPGA Bridges182 In this case, the FPGA Manager which programs the FPGA also handles the183 bridges behind the scenes. No FPGA Bridge devices are needed for full184 reconfiguration.185 186 * Full reconfiguration with hardware bridges187 In this case, there are hardware bridges between the processor and FPGA that188 need to be controlled during full reconfiguration. Before the overlay is189 applied, the live DT must include the FPGA Manager, FPGA Bridges, and a190 FPGA Region. The FPGA Region is the child of the bridge that allows191 register access to the FPGA. Additional bridges may be listed in a192 fpga-bridges property in the FPGA region or in the device tree overlay.193 194 * Partial reconfiguration with bridges in the FPGA195 In this case, the FPGA will have one or more PRR's that may be programmed196 separately while the rest of the FPGA can remain active. To manage this,197 bridges need to exist in the FPGA that can gate the buses going to each FPGA198 region while the buses are enabled for other sections. Before any partial199 reconfiguration can be done, a base FPGA image must be loaded which includes200 PRR's with FPGA bridges. The device tree should have an FPGA region for each201 PRR.202 203 Constraints204 ===========205 206 It is beyond the scope of this document to fully describe all the FPGA design207 constraints required to make partial reconfiguration work[1] [2] [3], but a few208 deserve quick mention.209 210 A persona must have boundary connections that line up with those of the partition211 or region it is designed to go into.212 213 During programming, transactions through those connections must be stopped and214 the connections must be held at a fixed logic level. This can be achieved by215 FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.216 217 --218 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf219 [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf220 [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf221 222properties:223 $nodename:224 pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"225 226 compatible:227 const: fpga-region228 229 reg:230 maxItems: 1231 232 ranges: true233 "#address-cells": true234 "#size-cells": true235 236 config-complete-timeout-us:237 description:238 The maximum time in microseconds time for the FPGA to go to operating239 mode after the region has been programmed.240 241 encrypted-fpga-config:242 type: boolean243 description:244 Set if the bitstream is encrypted.245 246 external-fpga-config:247 type: boolean248 description:249 Set if the FPGA has already been configured prior to OS boot up.250 251 firmware-name:252 maxItems: 1253 description:254 Should contain the name of an FPGA image file located on the firmware255 search path. If this property shows up in a live device tree it indicates256 that the FPGA has already been programmed with this image.257 If this property is in an overlay targeting an FPGA region, it is258 a request to program the FPGA with that image.259 260 fpga-bridges:261 $ref: /schemas/types.yaml#/definitions/phandle-array262 description:263 Should contain a list of phandles to FPGA Bridges that must be264 controlled during FPGA programming along with the parent FPGA bridge.265 This property is optional if the FPGA Manager handles the bridges.266 If the fpga-region is the child of an fpga-bridge, the list should not267 contain the parent bridge.268 269 fpga-mgr:270 $ref: /schemas/types.yaml#/definitions/phandle271 description:272 Should contain a phandle to an FPGA Manager. Child FPGA Regions273 inherit this property from their ancestor regions. An fpga-mgr property274 in a region will override any inherited FPGA manager.275 276 partial-fpga-config:277 type: boolean278 description:279 Set if partial reconfiguration is to be done, otherwise full280 reconfiguration is done.281 282 region-freeze-timeout-us:283 description:284 The maximum time in microseconds to wait for bridges to successfully285 become disabled before the region has been programmed.286 287 region-unfreeze-timeout-us:288 description:289 The maximum time in microseconds to wait for bridges to successfully290 become enabled after the region has been programmed.291 292required:293 - compatible294 - fpga-mgr295 296additionalProperties:297 type: object298 299examples:300 - |301 /*302 * Full Reconfiguration without Bridges with DT overlay303 */304 fpga_region0: fpga-region@0 {305 compatible = "fpga-region";306 reg = <0 0>;307 #address-cells = <1>;308 #size-cells = <1>;309 fpga-mgr = <&fpga_mgr0>;310 ranges = <0x10000000 0x20000000 0x10000000>;311 312 /* DT Overlay contains: &fpga_region0 */313 firmware-name = "zynq-gpio.bin";314 gpio@40000000 {315 compatible = "xlnx,xps-gpio-1.00.a";316 reg = <0x40000000 0x10000>;317 gpio-controller;318 #gpio-cells = <2>;319 };320 };321 322 - |323 /*324 * Partial reconfiguration with bridge325 */326 fpga_region1: fpga-region@0 {327 compatible = "fpga-region";328 reg = <0 0>;329 ranges;330 #address-cells = <1>;331 #size-cells = <1>;332 fpga-mgr = <&fpga_mgr1>;333 fpga-bridges = <&fpga_bridge1>;334 partial-fpga-config;335 336 /* DT Overlay contains: &fpga_region1 */337 firmware-name = "zynq-gpio-partial.bin";338 clk: clock {339 compatible = "fixed-factor-clock";340 clocks = <&parentclk>;341 #clock-cells = <0>;342 clock-div = <2>;343 clock-mult = <1>;344 };345 axi {346 compatible = "simple-bus";347 #address-cells = <1>;348 #size-cells = <1>;349 ranges;350 gpio@40000000 {351 compatible = "xlnx,xps-gpio-1.00.a";352 reg = <0x40000000 0x10000>;353 #gpio-cells = <2>;354 gpio-controller;355 clocks = <&clk>;356 };357 };358 };359