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1Lattice iCE40 FPGA Manager2 3Required properties:4- compatible: Should contain "lattice,ice40-fpga-mgr"5- reg: SPI chip select6- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)7- cdone-gpios: GPIO input connected to CDONE pin8- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note9 that unless the GPIO is held low during startup, the10 FPGA will enter Master SPI mode and drive SCK with a11 clock signal potentially jamming other devices on the12 bus until the firmware is loaded.13 14Example:15 fpga: fpga@0 {16 compatible = "lattice,ice40-fpga-mgr";17 reg = <0>;18 spi-max-frequency = <1000000>;19 cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;20 reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;21 };22