53 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx Zynq FPGA Manager8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12properties:13 compatible:14 const: xlnx,zynq-devcfg-1.015 16 reg:17 maxItems: 118 19 interrupts:20 maxItems: 121 22 clocks:23 maxItems: 124 25 clock-names:26 items:27 - const: ref_clk28 29 syscon:30 $ref: /schemas/types.yaml#/definitions/phandle31 description:32 Phandle to syscon block which provide access to SLCR registers33 34required:35 - compatible36 - reg37 - clocks38 - clock-names39 - syscon40 41additionalProperties: false42 43examples:44 - |45 devcfg: devcfg@f8007000 {46 compatible = "xlnx,zynq-devcfg-1.0";47 reg = <0xf8007000 0x100>;48 interrupts = <0 8 4>;49 clocks = <&clkc 12>;50 clock-names = "ref_clk";51 syscon = <&slcr>;52 };53