118 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Generic MMIO GPIO8 9maintainers:10 - Linus Walleij <linus.walleij@linaro.org>11 - Bartosz Golaszewski <brgl@bgdev.pl>12 13description:14 Some simple GPIO controllers may consist of a single data register or a pair15 of set/clear-bit registers. Such controllers are common for glue logic in16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped17 NAND-style parallel busses.18 19properties:20 compatible:21 enum:22 - brcm,bcm6345-gpio23 - ni,169445-nand-gpio24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller25 26 big-endian: true27 28 '#gpio-cells':29 const: 230 31 gpio-controller: true32 33 little-endian: true34 35 reg:36 minItems: 137 description:38 A list of registers in the controller. The width of each register is39 determined by its size. All registers must have the same width. The number40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.41 items:42 - description:43 Register to READ the value of the GPIO lines. If GPIO line is high,44 the bit will be set. If the GPIO line is low, the bit will be cleared.45 This register may also be used to drive GPIOs if the SET register is46 omitted.47 - description:48 Register to SET the value of the GPIO lines. Setting a bit in this49 register will drive the GPIO line high.50 - description:51 Register to CLEAR the value of the GPIO lines. Setting a bit in this52 register will drive the GPIO line low. If this register is omitted,53 the SET register will be used to clear the GPIO lines as well, by54 actively writing the line with 0.55 - description:56 Register to set the line as OUTPUT. Setting a bit in this register57 will turn that line into an output line. Conversely, clearing a bit58 will turn that line into an input.59 - description:60 Register to set this line as INPUT. Setting a bit in this register61 will turn that line into an input line. Conversely, clearing a bit62 will turn that line into an output.63 64 reg-names:65 minItems: 166 maxItems: 567 items:68 enum:69 - dat70 - set71 - clr72 - dirout73 - dirin74 75 native-endian: true76 77 no-output:78 $ref: /schemas/types.yaml#/definitions/flag79 description:80 If this property is present, the controller cannot drive the GPIO lines.81 82required:83 - compatible84 - reg85 - reg-names86 - '#gpio-cells'87 - gpio-controller88 89additionalProperties: false90 91examples:92 - |93 gpio@1f300010 {94 compatible = "ni,169445-nand-gpio";95 reg = <0x1f300010 0x4>;96 reg-names = "dat";97 gpio-controller;98 #gpio-cells = <2>;99 };100 101 gpio@e0100000 {102 compatible = "wd,mbl-gpio";103 reg-names = "dat";104 reg = <0xe0100000 0x1>;105 #gpio-cells = <2>;106 gpio-controller;107 no-output;108 };109 110 gpio@fffe0406 {111 compatible = "brcm,bcm6345-gpio";112 reg-names = "dirout", "dat";113 reg = <0xfffe0406 2>, <0xfffe040a 2>;114 native-endian;115 gpio-controller;116 #gpio-cells = <2>;117 };118