brintos

brintos / linux-shallow public Read only

0
0
Text · 3.2 KiB · 33d4e47 Raw
147 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Marvell EBU GPIO controller8 9maintainers:10  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>11  - Andrew Lunn <andrew@lunn.ch>12 13properties:14  compatible:15    oneOf:16      - enum:17          - marvell,armada-8k-gpio18          - marvell,orion-gpio19 20      - items:21          - enum:22              - marvell,mv78200-gpio23              - marvell,armada-370-gpio24          - const: marvell,orion-gpio25 26      - description: Deprecated binding27        items:28          - const: marvell,armadaxp-gpio29          - const: marvell,orion-gpio30        deprecated: true31 32  reg:33    description: |34      Address and length of the register set for the device. Not used for35      marvell,armada-8k-gpio.36 37      A second entry can be provided, for the PWM function using the GPIO Blink38      Counter on/off registers.39    minItems: 140    maxItems: 241 42  reg-names:43    items:44      - const: gpio45      - const: pwm46    minItems: 147 48  offset:49    $ref: /schemas/types.yaml#/definitions/uint3250    description: Offset in the register map for the gpio registers (in bytes)51 52  interrupts:53    description: |54      The list of interrupts that are used for all the pins managed by this55      GPIO bank. There can be more than one interrupt (example: 1 interrupt56      per 8 pins on Armada XP, which means 4 interrupts per bank of 3257      GPIOs).58    minItems: 159    maxItems: 460 61  interrupt-controller: true62 63  "#interrupt-cells":64    const: 265 66  gpio-controller: true67 68  ngpios:69    minimum: 170    maximum: 3271 72  "#gpio-cells":73    const: 274 75  marvell,pwm-offset:76    $ref: /schemas/types.yaml#/definitions/uint3277    description: Offset in the register map for the pwm registers (in bytes)78 79  "#pwm-cells":80    description:81      The first cell is the GPIO line number. The second cell is the period82      in nanoseconds.83    const: 284 85  clocks:86    description:87      Clock(s) used for PWM function.88    items:89      - description: Core clock90      - description: AXI bus clock91    minItems: 192 93  clock-names:94    items:95      - const: core96      - const: axi97    minItems: 198 99required:100  - compatible101  - gpio-controller102  - ngpios103  - "#gpio-cells"104 105allOf:106  - if:107      properties:108        compatible:109          contains:110            const: marvell,armada-8k-gpio111    then:112      required:113        - offset114    else:115      required:116        - reg117 118unevaluatedProperties: false119 120examples:121  - |122    gpio@d0018100 {123      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";124      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;125      ngpios = <32>;126      gpio-controller;127      #gpio-cells = <2>;128      interrupt-controller;129      #interrupt-cells = <2>;130      interrupts = <16>, <17>, <18>, <19>;131    };132 133  - |134    gpio@18140 {135      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";136      reg = <0x18140 0x40>, <0x181c8 0x08>;137      reg-names = "gpio", "pwm";138      ngpios = <17>;139      gpio-controller;140      #gpio-cells = <2>;141      #pwm-cells = <2>;142      interrupt-controller;143      #interrupt-cells = <2>;144      interrupts = <87>, <88>, <89>;145      clocks = <&coreclk 0>;146    };147