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1Specifying GPIO information for devices2=======================================3 41) gpios property5-----------------6 7GPIO properties should be named "[<name>-]gpios", with <name> being the purpose8of this GPIO for the device. While a non-existent <name> is considered valid9for compatibility reasons (resolving to the "gpios" property), it is not allowed10for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old11bindings use it, but are only supported for compatibility reasons and should not12be used for newer bindings since it has been deprecated.13 14GPIO properties can contain one or more GPIO phandles, but only in exceptional15cases should they contain more than one. If your device uses several GPIOs with16distinct functions, reference each of them under its own property, giving it a17meaningful name. The only case where an array of GPIOs is accepted is when18several GPIOs serve the same function (e.g. a parallel data line).19 20The exact purpose of each gpios property must be documented in the device tree21binding of the device.22 23The following example could be used to describe GPIO pins used as device enable24and bit-banged data signals:25 26 gpio1: gpio1 {27 gpio-controller;28 #gpio-cells = <2>;29 };30 [...]31 32 data-gpios = <&gpio1 12 0>,33 <&gpio1 13 0>,34 <&gpio1 14 0>,35 <&gpio1 15 0>;36 37In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is38a local offset to the GPIO line and the second cell represent consumer flags,39such as if the consumer desire the line to be active low (inverted) or open40drain. This is the recommended practice.41 42The exact meaning of each specifier cell is controller specific, and must be43documented in the device tree binding for the device, but it is strongly44recommended to use the two-cell approach.45 46Most controllers are specifying a generic flag bitfield in the last cell, so47for these, use the macros defined in48include/dt-bindings/gpio/gpio.h whenever possible:49 50Example of a node using GPIOs:51 52 node {53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;54 };55 56GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes57GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.58 59Optional standard bitfield specifiers for the last cell:60 61- Bit 0: 0 means active high, 1 means active low62- Bit 1: 0 mean push-pull wiring, see:63 https://en.wikipedia.org/wiki/Push-pull_output64 1 means single-ended wiring, see:65 https://en.wikipedia.org/wiki/Single-ended_triode66- Bit 2: 0 means open-source, 1 means open drain, see:67 https://en.wikipedia.org/wiki/Open_collector68- Bit 3: 0 means the output should be maintained during sleep/low-power mode69 1 means the output state can be lost during sleep/low-power mode70- Bit 4: 0 means no pull-up resistor should be enabled71 1 means a pull-up resistor should be enabled72 This setting only applies to hardware with a simple on/off73 control for pull-up configuration. If the hardware has more74 elaborate pull-up configuration, it should be represented75 using a pin control binding.76- Bit 5: 0 means no pull-down resistor should be enabled77 1 means a pull-down resistor should be enabled78 This setting only applies to hardware with a simple on/off79 control for pull-down configuration. If the hardware has more80 elaborate pull-down configuration, it should be represented81 using a pin control binding.82 831.1) GPIO specifier best practices84----------------------------------85 86A gpio-specifier should contain a flag indicating the GPIO polarity; active-87high or active-low. If it does, the following best practices should be88followed:89 90The gpio-specifier's polarity flag should represent the physical level at the91GPIO controller that achieves (or represents, for inputs) a logically asserted92value at the device. The exact definition of logically asserted should be93defined by the binding for the device. If the board inverts the signal between94the GPIO controller and the device, then the gpio-specifier will represent the95opposite physical level than the signal at the device's pin.96 97When the device's signal polarity is configurable, the binding for the98device must either:99 100a) Define a single static polarity for the signal, with the expectation that101any software using that binding would statically program the device to use102that signal polarity.103 104The static choice of polarity may be either:105 106a1) (Preferred) Dictated by a binding-specific DT property.107 108or:109 110a2) Defined statically by the DT binding itself.111 112In particular, the polarity cannot be derived from the gpio-specifier, since113that would prevent the DT from separately representing the two orthogonal114concepts of configurable signal polarity in the device, and possible board-115level signal inversion.116 117or:118 119b) Pick a single option for device signal polarity, and document this choice120in the binding. The gpio-specifier should represent the polarity of the signal121(at the GPIO controller) assuming that the device is configured for this122particular signal polarity choice. If software chooses to program the device123to generate or receive a signal of the opposite polarity, software will be124responsible for correctly interpreting (inverting) the GPIO signal at the GPIO125controller.126 1272) gpio-controller nodes128------------------------129 130Every GPIO controller node must contain both an empty "gpio-controller"131property, and a #gpio-cells integer property, which indicates the number of132cells in a gpio-specifier.133 134Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an135instance of a hardware IP core on a silicon die, usually exposed to the136programmer as a coherent range of I/O addresses. Usually each such bank is137exposed in the device tree as an individual gpio-controller node, reflecting138the fact that the hardware was synthesized by reusing the same IP block a139few times over.140 141Optionally, a GPIO controller may have a "ngpios" property. This property142indicates the number of in-use slots of available slots for GPIOs. The143typical example is something like this: the hardware register is 32 bits144wide, but only 18 of the bits have a physical counterpart. The driver is145generally written so that all 32 bits can be used, but the IP block is reused146in a lot of designs, some using all 32 bits, some using 18 and some using14712. In this case, setting "ngpios = <18>;" informs the driver that only the148first 18 GPIOs, at local offset 0 .. 17, are in use.149 150If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an151additional set of tuples is needed to specify which GPIOs are unusable, with152the gpio-reserved-ranges binding. This property indicates the start and size153of the GPIOs that can't be used.154 155Optionally, a GPIO controller may have a "gpio-line-names" property. This is156an array of strings defining the names of the GPIO lines going out of the157GPIO controller.158 159For lines which are routed to on-board devices, this name should be160the most meaningful producer name for the system, such as a rail name161indicating the usage. Package names, such as a pin name, are discouraged:162such lines have opaque names (since they are by definition general-purpose)163and such names are usually not very helpful. For example "MMC-CD", "Red LED164Vdd" and "ethernet reset" are reasonable line names as they describe what165the line is used for. "GPIO0" is not a good name to give to a GPIO line166that is hard-wired to a specific device.167 168However, in the case of lines that are routed to a general purpose header169(e.g. the Raspberry Pi 40-pin header), and therefore are not hard-wired to170specific devices, using a pin number or the names on the header is fine171provided these are real (preferably unique) names. Using an SoC's pad name172or package name, or names made up from kernel-internal software constructs,173are strongly discouraged. For example "pin8 [gpio14/uart0_txd]" is fine174if the board's documentation labels pin 8 as such. However "PortB_24" (an175example of a name from an SoC's reference manual) would not be desirable.176 177In either case placeholders are discouraged: rather use the "" (blank178string) if the use of the GPIO line is undefined in your design. Ideally,179try to add comments to the dts file describing the naming the convention180you have chosen, and specifying from where the names are derived.181 182The names are assigned starting from line offset 0, from left to right,183from the passed array. An incomplete array (where the number of passed184names is less than ngpios) will be used up until the last provided valid185line index.186 187Example:188 189gpio-controller@00000000 {190 compatible = "foo";191 reg = <0x00000000 0x1000>;192 gpio-controller;193 #gpio-cells = <2>;194 ngpios = <18>;195 gpio-reserved-ranges = <0 4>, <12 2>;196 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",197 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",198 "Row A", "Row B", "Row C", "Row D", "NMI button",199 "poweroff", "reset";200}201 202The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism203providing automatic GPIO request and configuration as part of the204gpio-controller's driver probe function.205 206Each GPIO hog definition is represented as a child node of the GPIO controller.207Required properties:208- gpio-hog: A property specifying that this child node represents a GPIO hog.209- gpios: Store the GPIO information (id, flags, ...) for each GPIO to210 affect. Shall contain an integer multiple of the number of cells211 specified in its parent node (GPIO controller node).212Only one of the following properties scanned in the order shown below.213This means that when multiple properties are present they will be searched214in the order presented below and the first match is taken as the intended215configuration.216- input: A property specifying to set the GPIO direction as input.217- output-low A property specifying to set the GPIO direction as output with218 the value low.219- output-high A property specifying to set the GPIO direction as output with220 the value high.221 222Optional properties:223- line-name: The GPIO label name. If not present the node name is used.224 225Example of two SOC GPIO banks defined as gpio-controller nodes:226 227 qe_pio_a: gpio-controller@1400 {228 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";229 reg = <0x1400 0x18>;230 gpio-controller;231 #gpio-cells = <2>;232 233 line_b-hog {234 gpio-hog;235 gpios = <6 0>;236 output-low;237 line-name = "foo-bar-gpio";238 };239 };240 241 qe_pio_e: gpio-controller@1460 {242 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";243 reg = <0x1460 0x18>;244 gpio-controller;245 #gpio-cells = <2>;246 };247 2482.1) gpio- and pin-controller interaction249-----------------------------------------250 251Some or all of the GPIOs provided by a GPIO controller may be routed to pins252on the package via a pin controller. This allows muxing those pins between253GPIO and other functions. It is a fairly common practice among silicon254engineers.255 2562.2) Ordinary (numerical) GPIO ranges257-------------------------------------258 259It is useful to represent which GPIOs correspond to which pins on which pin260controllers. The gpio-ranges property described below represents this with261a discrete set of ranges mapping pins from the pin controller local number space262to pins in the GPIO controller local number space.263 264The format is: <[pin controller phandle], [GPIO controller offset],265 [pin controller offset], [number of pins]>;266 267The GPIO controller offset pertains to the GPIO controller node containing the268range definition.269 270The pin controller node referenced by the phandle must conform to the bindings271described in pinctrl/pinctrl-bindings.txt.272 273Each offset runs from 0 to N. It is perfectly fine to pile any number of274ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but275in practice these ranges are often lumped in discrete sets.276 277Example:278 279 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;280 281This means:282- pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and283- pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29284 285 286Verbose example:287 288 qe_pio_e: gpio-controller@1460 {289 #gpio-cells = <2>;290 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";291 reg = <0x1460 0x18>;292 gpio-controller;293 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;294 };295 296Here, a single GPIO controller has GPIOs 0..9 routed to pin controller297pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's298pins 50..69.299 300 3012.3) GPIO ranges from named pin groups302--------------------------------------303 304It is also possible to use pin groups for gpio ranges when pin groups are the305easiest and most convenient mapping.306 307Both both <pinctrl-base> and <count> must set to 0 when using named pin groups308names.309 310The property gpio-ranges-group-names must contain exactly one string for each311range.312 313Elements of gpio-ranges-group-names must contain the name of a pin group314defined in the respective pin controller. The number of pins/GPIO lines in the315range is the number of pins in that pin group. The number of pins of that316group is defined int the implementation and not in the device tree.317 318If numerical and named pin groups are mixed, the string corresponding to a319numerical pin range in gpio-ranges-group-names must be empty.320 321Example:322 323 gpio_pio_i: gpio-controller@14b0 {324 #gpio-cells = <2>;325 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";326 reg = <0x1480 0x18>;327 gpio-controller;328 gpio-ranges = <&pinctrl1 0 20 10>,329 <&pinctrl2 10 0 0>,330 <&pinctrl1 15 0 10>,331 <&pinctrl2 25 0 0>;332 gpio-ranges-group-names = "",333 "foo",334 "",335 "bar";336 };337 338Here, three GPIO ranges are defined referring to two pin controllers.339 340pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges341in pinctrl2 are defined using the pin groups named "foo" and "bar".342 343Previous versions of this binding required all pin controller nodes that344were referenced by any gpio-ranges property to contain a property named345#gpio-range-cells with value <3>. This requirement is now deprecated.346However, that property may still exist in older device trees for347compatibility reasons, and would still be required even in new device348trees that need to be compatible with older software.349