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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 compatible:15 oneOf:16 - enum:17 - nvidia,tegra20-gpio18 - nvidia,tegra30-gpio19 20 - items:21 - enum:22 - nvidia,tegra114-gpio23 - nvidia,tegra124-gpio24 - nvidia,tegra210-gpio25 - const: nvidia,tegra30-gpio26 27 reg:28 maxItems: 129 30 interrupts:31 description: The interrupt outputs from the controller. For Tegra20,32 there should be 7 interrupts specified, and for Tegra30, there should33 be 8 interrupts specified.34 35 "#gpio-cells":36 description: The first cell is the pin number and the second cell is used37 to specify the GPIO polarity (0 = active high, 1 = active low).38 const: 239 40 gpio-controller: true41 42 gpio-ranges:43 maxItems: 144 45 "#interrupt-cells":46 description: |47 Should be 2. The first cell is the GPIO number. The second cell is48 used to specify flags:49 50 bits[3:0] trigger type and level flags:51 1 = low-to-high edge triggered.52 2 = high-to-low edge triggered.53 4 = active high level-sensitive.54 8 = active low level-sensitive.55 56 Valid combinations are 1, 2, 3, 4, 8.57 const: 258 59 interrupt-controller: true60 61allOf:62 - if:63 properties:64 compatible:65 contains:66 const: nvidia,tegra30-gpio67 then:68 properties:69 interrupts:70 minItems: 871 maxItems: 872 else:73 properties:74 interrupts:75 minItems: 776 maxItems: 777 78required:79 - compatible80 - reg81 - interrupts82 - "#gpio-cells"83 - gpio-controller84 - "#interrupt-cells"85 - interrupt-controller86 87additionalProperties:88 type: object89 required:90 - gpio-hog91 92examples:93 - |94 #include <dt-bindings/interrupt-controller/arm-gic.h>95 96 gpio: gpio@6000d000 {97 compatible = "nvidia,tegra20-gpio";98 reg = <0x6000d000 0x1000>;99 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,100 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,101 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,102 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,103 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,104 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,105 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;106 #gpio-cells = <2>;107 gpio-controller;108 #interrupt-cells = <2>;109 interrupt-controller;110 };111