97 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip GPIO bank8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12properties:13 compatible:14 enum:15 - rockchip,gpio-bank16 - rockchip,rk3188-gpio-bank017 18 reg:19 maxItems: 120 21 interrupts:22 maxItems: 123 24 clocks:25 minItems: 126 items:27 - description: APB interface clock source28 - description: GPIO debounce reference clock source29 30 gpio-ranges: true31 32 gpio-controller: true33 34 gpio-line-names: true35 36 "#gpio-cells":37 const: 238 39 interrupt-controller: true40 41 "#interrupt-cells":42 const: 243 44patternProperties:45 "^.+-hog(-[0-9]+)?$":46 type: object47 48 required:49 - gpio-hog50 51required:52 - compatible53 - reg54 - interrupts55 - clocks56 - gpio-controller57 - "#gpio-cells"58 - interrupt-controller59 - "#interrupt-cells"60 61additionalProperties: false62 63examples:64 - |65 #include <dt-bindings/interrupt-controller/arm-gic.h>66 pinctrl: pinctrl {67 #address-cells = <1>;68 #size-cells = <1>;69 ranges;70 71 gpio0: gpio@2000a000 {72 compatible = "rockchip,rk3188-gpio-bank0";73 reg = <0x2000a000 0x100>;74 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;75 clocks = <&clk_gates8 9>;76 77 gpio-controller;78 #gpio-cells = <2>;79 80 interrupt-controller;81 #interrupt-cells = <2>;82 };83 84 gpio1: gpio@2003c000 {85 compatible = "rockchip,gpio-bank";86 reg = <0x2003c000 0x100>;87 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;88 clocks = <&clk_gates8 10>;89 90 gpio-controller;91 #gpio-cells = <2>;92 93 interrupt-controller;94 #interrupt-cells = <2>;95 };96 };97