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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx AXI GPIO controller8 9maintainers:10 - Neeli Srinivas <srinivas.neeli@amd.com>11 12description:13 The AXI GPIO design provides a general purpose input/output interface14 to an AXI4-Lite interface. The AXI GPIO can be configured as either15 a single or a dual-channel device. The width of each channel is16 independently configurable. The channels can be configured to17 generate an interrupt when a transition on any of their inputs occurs.18 19properties:20 compatible:21 enum:22 - xlnx,xps-gpio-1.00.a23 24 reg:25 maxItems: 126 27 "#gpio-cells":28 const: 229 30 interrupts:31 maxItems: 132 33 gpio-controller: true34 35 gpio-line-names:36 description: strings describing the names of each gpio line37 minItems: 138 maxItems: 6439 40 interrupt-controller: true41 42 "#interrupt-cells":43 const: 244 45 clocks:46 maxItems: 147 48 interrupt-names: true49 50 xlnx,all-inputs:51 $ref: /schemas/types.yaml#/definitions/uint3252 description: This option sets this GPIO channel1 bits in input mode.53 54 xlnx,all-inputs-2:55 $ref: /schemas/types.yaml#/definitions/uint3256 description: This option sets this GPIO channel2 bits in input mode.57 58 xlnx,all-outputs:59 $ref: /schemas/types.yaml#/definitions/uint3260 description: This option sets this GPIO channel1 bits in output mode.61 62 xlnx,all-outputs-2:63 $ref: /schemas/types.yaml#/definitions/uint3264 description: This option sets this GPIO channel2 bits in output mode.65 66 xlnx,dout-default:67 $ref: /schemas/types.yaml#/definitions/uint3268 description: Sets the default value of all the enabled bits of69 channel1.70 default: 071 72 xlnx,dout-default-2:73 $ref: /schemas/types.yaml#/definitions/uint3274 description: Sets the default value of all the enabled bits of75 channel2.76 default: 077 78 xlnx,gpio-width:79 $ref: /schemas/types.yaml#/definitions/uint3280 description: The value defines the bit width of the GPIO channel1.81 minimum: 182 maximum: 3283 default: 3284 85 xlnx,gpio2-width:86 $ref: /schemas/types.yaml#/definitions/uint3287 description: The value defines the bit width of the GPIO channel2.88 minimum: 189 maximum: 3290 default: 3291 92 xlnx,interrupt-present:93 $ref: /schemas/types.yaml#/definitions/uint3294 description: This parameter enables interrupt control logic95 and interrupt registers in GPIO module.96 minimum: 097 maximum: 198 default: 099 100 xlnx,is-dual:101 $ref: /schemas/types.yaml#/definitions/uint32102 description: This parameter enables a second GPIO channel (GPIO2).103 minimum: 0104 maximum: 1105 default: 0106 107 xlnx,tri-default:108 $ref: /schemas/types.yaml#/definitions/uint32109 description: This value configures the input or output mode110 of each bit of GPIO channel1.111 112 xlnx,tri-default-2:113 $ref: /schemas/types.yaml#/definitions/uint32114 description: This value configures the input or output mode115 of each bit of GPIO channel2.116 117required:118 - reg119 - compatible120 - gpio-controller121 - "#gpio-cells"122 123unevaluatedProperties: false124 125examples:126 - |127 #include <dt-bindings/interrupt-controller/arm-gic.h>128 129 gpio@a0020000 {130 compatible = "xlnx,xps-gpio-1.00.a";131 reg = <0xa0020000 0x10000>;132 #gpio-cells = <2>;133 #interrupt-cells = <0x2>;134 clocks = <&zynqmp_clk 71>;135 gpio-controller;136 interrupt-controller;137 interrupt-names = "ip2intc_irpt";138 interrupt-parent = <&gic>;139 interrupts = <0 89 4>;140 xlnx,all-inputs = <0x0>;141 xlnx,all-inputs-2 = <0x0>;142 xlnx,all-outputs = <0x0>;143 xlnx,all-outputs-2 = <0x0>;144 xlnx,dout-default = <0x0>;145 xlnx,dout-default-2 = <0x0>;146 xlnx,gpio-width = <0x20>;147 xlnx,gpio2-width = <0x20>;148 xlnx,interrupt-present = <0x1>;149 xlnx,is-dual = <0x1>;150 xlnx,tri-default = <0xFFFFFFFF>;151 xlnx,tri-default-2 = <0xFFFFFFFF>;152 };153 154...155