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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM Mali Utgard GPU8 9maintainers:10 - Rob Herring <robh@kernel.org>11 - Maxime Ripard <mripard@kernel.org>12 - Heiko Stuebner <heiko@sntech.de>13 14properties:15 $nodename:16 pattern: '^gpu@[a-f0-9]+$'17 compatible:18 oneOf:19 - items:20 - const: allwinner,sun8i-a23-mali21 - const: allwinner,sun7i-a20-mali22 - const: arm,mali-40023 - items:24 - enum:25 - allwinner,sun4i-a10-mali26 - allwinner,sun7i-a20-mali27 - allwinner,sun8i-h3-mali28 - allwinner,sun8i-r40-mali29 - allwinner,sun50i-a64-mali30 - rockchip,rk3036-mali31 - rockchip,rk3066-mali32 - rockchip,rk3128-mali33 - rockchip,rk3188-mali34 - rockchip,rk3228-mali35 - samsung,exynos4210-mali36 - stericsson,db8500-mali37 - xlnx,zynqmp-mali38 - const: arm,mali-40039 - items:40 - enum:41 - allwinner,sun50i-h5-mali42 - amlogic,meson8-mali43 - amlogic,meson8b-mali44 - amlogic,meson-gxbb-mali45 - amlogic,meson-gxl-mali46 - hisilicon,hi6220-mali47 - mediatek,mt7623-mali48 - rockchip,rk3328-mali49 - const: arm,mali-45050 51 # "arm,mali-300"52 53 reg:54 maxItems: 155 56 interrupts:57 minItems: 458 maxItems: 2059 60 interrupt-names:61 allOf:62 - additionalItems: true63 minItems: 464 maxItems: 2065 items:66 # At least enforce the first 2 interrupts67 - const: gp68 - const: gpmmu69 - items:70 # Not ideal as any order and combination are allowed71 enum:72 - gp # Geometry Processor interrupt73 - gpmmu # Geometry Processor MMU interrupt74 - pp # Pixel Processor broadcast interrupt (mali-450 only)75 - pp0 # Pixel Processor X interrupt (X from 0 to 7)76 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)77 - pp178 - ppmmu179 - pp280 - ppmmu281 - pp382 - ppmmu383 - pp484 - ppmmu485 - pp586 - ppmmu587 - pp688 - ppmmu689 - pp790 - ppmmu791 - pmu # Power Management Unit interrupt (optional)92 - combined # stericsson,db8500-mali only93 94 clocks:95 maxItems: 296 97 clock-names:98 items:99 - const: bus100 - const: core101 102 memory-region: true103 104 mali-supply: true105 106 opp-table:107 type: object108 109 power-domains:110 maxItems: 1111 112 resets:113 maxItems: 1114 115 operating-points-v2: true116 117 "#cooling-cells":118 const: 2119 120required:121 - compatible122 - reg123 - interrupts124 - interrupt-names125 - clocks126 - clock-names127 128additionalProperties: false129 130allOf:131 - if:132 properties:133 compatible:134 contains:135 enum:136 - allwinner,sun4i-a10-mali137 - allwinner,sun7i-a20-mali138 - allwinner,sun8i-r40-mali139 - allwinner,sun50i-a64-mali140 - allwinner,sun50i-h5-mali141 - amlogic,meson8-mali142 - amlogic,meson8b-mali143 - hisilicon,hi6220-mali144 - mediatek,mt7623-mali145 - rockchip,rk3036-mali146 - rockchip,rk3066-mali147 - rockchip,rk3188-mali148 - rockchip,rk3228-mali149 - rockchip,rk3328-mali150 then:151 required:152 - resets153 154examples:155 - |156 #include <dt-bindings/interrupt-controller/irq.h>157 #include <dt-bindings/interrupt-controller/arm-gic.h>158 159 mali: gpu@1c40000 {160 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";161 reg = <0x01c40000 0x10000>;162 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,163 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,164 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,165 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,166 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,167 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,168 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;169 interrupt-names = "gp",170 "gpmmu",171 "pp0",172 "ppmmu0",173 "pp1",174 "ppmmu1",175 "pmu";176 clocks = <&ccu 1>, <&ccu 2>;177 clock-names = "bus", "core";178 resets = <&ccu 1>;179 #cooling-cells = <2>;180 };181 182...183