107 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra NVDEC8 9description: |10 NVDEC is the hardware video decoder present on NVIDIA Tegra21011 and newer chips. It is located on the Host1x bus and typically12 programmed through Host1x channels.13 14maintainers:15 - Thierry Reding <treding@gmail.com>16 - Mikko Perttunen <mperttunen@nvidia.com>17 18properties:19 $nodename:20 pattern: "^nvdec@[0-9a-f]*$"21 22 compatible:23 enum:24 - nvidia,tegra210-nvdec25 - nvidia,tegra186-nvdec26 - nvidia,tegra194-nvdec27 28 reg:29 maxItems: 130 31 clocks:32 maxItems: 133 34 clock-names:35 items:36 - const: nvdec37 38 resets:39 maxItems: 140 41 reset-names:42 items:43 - const: nvdec44 45 power-domains:46 maxItems: 147 48 iommus:49 maxItems: 150 51 dma-coherent: true52 53 interconnects:54 items:55 - description: DMA read memory client56 - description: DMA read 2 memory client57 - description: DMA write memory client58 59 interconnect-names:60 items:61 - const: dma-mem62 - const: read-163 - const: write64 65 nvidia,host1x-class:66 description: |67 Host1x class of the engine, used to specify the targeted engine68 when programming the engine through Host1x channels or when69 configuring engine-specific behavior in Host1x.70 default: 0xf071 $ref: /schemas/types.yaml#/definitions/uint3272 73required:74 - compatible75 - reg76 - clocks77 - clock-names78 - resets79 - reset-names80 - power-domains81 82additionalProperties: false83 84examples:85 - |86 #include <dt-bindings/clock/tegra186-clock.h>87 #include <dt-bindings/interrupt-controller/arm-gic.h>88 #include <dt-bindings/memory/tegra186-mc.h>89 #include <dt-bindings/power/tegra186-powergate.h>90 #include <dt-bindings/reset/tegra186-reset.h>91 92 nvdec@15480000 {93 compatible = "nvidia,tegra186-nvdec";94 reg = <0x15480000 0x40000>;95 clocks = <&bpmp TEGRA186_CLK_NVDEC>;96 clock-names = "nvdec";97 resets = <&bpmp TEGRA186_RESET_NVDEC>;98 reset-names = "nvdec";99 100 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;101 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,102 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,103 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;104 interconnect-names = "dma-mem", "read-1", "write";105 iommus = <&smmu TEGRA186_SID_NVDEC>;106 };107