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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra234 NVDEC8 9description: |10 NVDEC is the hardware video decoder present on NVIDIA Tegra21011 and newer chips. It is located on the Host1x bus and typically12 programmed through Host1x channels.13 14maintainers:15 - Thierry Reding <treding@gmail.com>16 - Mikko Perttunen <mperttunen@nvidia.com>17 18properties:19 $nodename:20 pattern: "^nvdec@[0-9a-f]*$"21 22 compatible:23 enum:24 - nvidia,tegra234-nvdec25 26 reg:27 maxItems: 128 29 clocks:30 maxItems: 331 32 clock-names:33 items:34 - const: nvdec35 - const: fuse36 - const: tsec_pka37 38 resets:39 maxItems: 140 41 reset-names:42 items:43 - const: nvdec44 45 power-domains:46 maxItems: 147 48 iommus:49 maxItems: 150 51 dma-coherent: true52 53 interconnects:54 items:55 - description: DMA read memory client56 - description: DMA write memory client57 58 interconnect-names:59 items:60 - const: dma-mem61 - const: write62 63 nvidia,memory-controller:64 $ref: /schemas/types.yaml#/definitions/phandle65 description:66 phandle to the memory controller for determining information for the NVDEC67 firmware secure carveout. This carveout is configured by the bootloader and68 not accessible to CPU.69 70 nvidia,bl-manifest-offset:71 $ref: /schemas/types.yaml#/definitions/uint3272 description:73 Offset to bootloader manifest from beginning of firmware that was configured by74 the bootloader.75 76 nvidia,bl-code-offset:77 $ref: /schemas/types.yaml#/definitions/uint3278 description:79 Offset to bootloader code section from beginning of firmware that was configured by80 the bootloader.81 82 nvidia,bl-data-offset:83 $ref: /schemas/types.yaml#/definitions/uint3284 description:85 Offset to bootloader data section from beginning of firmware that was configured by86 the bootloader.87 88 nvidia,os-manifest-offset:89 $ref: /schemas/types.yaml#/definitions/uint3290 description:91 Offset to operating system manifest from beginning of firmware that was configured by92 the bootloader.93 94 nvidia,os-code-offset:95 $ref: /schemas/types.yaml#/definitions/uint3296 description:97 Offset to operating system code section from beginning of firmware that was configured by98 the bootloader.99 100 nvidia,os-data-offset:101 $ref: /schemas/types.yaml#/definitions/uint32102 description:103 Offset to operating system data section from beginning of firmware that was configured104 by the bootloader.105 106required:107 - compatible108 - reg109 - clocks110 - clock-names111 - resets112 - reset-names113 - power-domains114 - nvidia,memory-controller115 - nvidia,bl-manifest-offset116 - nvidia,bl-code-offset117 - nvidia,bl-data-offset118 - nvidia,os-manifest-offset119 - nvidia,os-code-offset120 - nvidia,os-data-offset121 122additionalProperties: false123 124examples:125 - |126 #include <dt-bindings/clock/tegra234-clock.h>127 #include <dt-bindings/memory/tegra234-mc.h>128 #include <dt-bindings/power/tegra234-powergate.h>129 #include <dt-bindings/reset/tegra234-reset.h>130 131 nvdec@15480000 {132 compatible = "nvidia,tegra234-nvdec";133 reg = <0x15480000 0x00040000>;134 clocks = <&bpmp TEGRA234_CLK_NVDEC>,135 <&bpmp TEGRA234_CLK_FUSE>,136 <&bpmp TEGRA234_CLK_TSEC_PKA>;137 clock-names = "nvdec", "fuse", "tsec_pka";138 resets = <&bpmp TEGRA234_RESET_NVDEC>;139 reset-names = "nvdec";140 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;141 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,142 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;143 interconnect-names = "dma-mem", "write";144 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;145 dma-coherent;146 147 nvidia,memory-controller = <&mc>;148 149 /* Placeholder values, to be replaced with values from overlay */150 nvidia,bl-manifest-offset = <0>;151 nvidia,bl-data-offset = <0>;152 nvidia,bl-code-offset = <0>;153 nvidia,os-manifest-offset = <0>;154 nvidia,os-data-offset = <0>;155 nvidia,os-code-offset = <0>;156 };157