76 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence I2C controller8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12allOf:13 - $ref: /schemas/i2c/i2c-controller.yaml#14 15properties:16 compatible:17 enum:18 - cdns,i2c-r1p10 # cadence i2c controller version 1.019 - cdns,i2c-r1p14 # cadence i2c controller version 1.420 21 reg:22 maxItems: 123 24 clocks:25 minItems: 126 27 resets:28 maxItems: 129 30 interrupts:31 maxItems: 132 33 clock-frequency:34 minimum: 135 maximum: 40000036 description: |37 Desired operating frequency, in Hz, of the bus.38 39 clock-name:40 const: pclk41 description: |42 Input clock name.43 44 fifo-depth:45 description:46 Size of the data FIFO in bytes.47 $ref: /schemas/types.yaml#/definitions/uint3248 default: 1649 enum: [2, 4, 8, 16, 32, 64, 128, 256]50 51 power-domains:52 maxItems: 153 54required:55 - compatible56 - reg57 - clocks58 - interrupts59 60unevaluatedProperties: false61 62examples:63 - |64 #include <dt-bindings/interrupt-controller/arm-gic.h>65 i2c@e0004000 {66 compatible = "cdns,i2c-r1p10";67 clocks = <&clkc 38>;68 resets = <&rstc 288>;69 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;70 reg = <0xe0004000 0x1000>;71 clock-frequency = <400000>;72 #address-cells = <1>;73 #size-cells = <0>;74 fifo-depth = <8>;75 };76