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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7maintainers:8 - Thierry Reding <thierry.reding@gmail.com>9 - Jon Hunter <jonathanh@nvidia.com>10 11title: NVIDIA Tegra I2C controller driver12 13properties:14 compatible:15 oneOf:16 - description: Tegra20 has 4 generic I2C controller. This can support17 master and slave mode of I2C communication. The i2c-tegra driver18 only support master mode of I2C communication. Driver of I2C19 controller is only compatible with "nvidia,tegra20-i2c".20 const: nvidia,tegra20-i2c21 - description: Tegra20 has specific I2C controller called as DVC I2C22 controller. This only support master mode of I2C communication.23 Register interface/offset and interrupts handling are different than24 generic I2C controller. Driver of DVC I2C controller is only25 compatible with "nvidia,tegra20-i2c-dvc".26 const: nvidia,tegra20-i2c-dvc27 - description: |28 Tegra30 has 5 generic I2C controller. This controller is very much29 similar to Tegra20 I2C controller with additional feature: Continue30 Transfer Support. This feature helps to implement M_NO_START as per31 I2C core API transfer flags. Driver of I2C controller is compatible32 with "nvidia,tegra30-i2c" to enable the continue transfer support.33 This is also compatible with "nvidia,tegra20-i2c" without continue34 transfer support.35 items:36 - const: nvidia,tegra30-i2c37 - const: nvidia,tegra20-i2c38 - description: |39 Tegra114 has 5 generic I2C controllers. This controller is very much40 similar to Tegra30 I2C controller with some hardware modification:41 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk42 and fast-clk. Tegra114 has only one clock source called as43 div-clk and hence clock mechanism is changed in I2C controller.44 - Tegra30/Tegra20 I2C controller has enabled per packet transfer45 by default and there is no way to disable it. Tegra114 has this46 interrupt disable by default and SW need to enable explicitly.47 Due to above changes, Tegra114 I2C driver makes incompatible with48 previous hardware driver. Hence, Tegra114 I2C controller is49 compatible with "nvidia,tegra114-i2c".50 const: nvidia,tegra114-i2c51 - description: |52 Tegra124 has 6 generic I2C controllers. These controllers are very53 similar to those found on Tegra114 but also contain several hardware54 improvements and new registers.55 const: nvidia,tegra124-i2c56 - description: |57 Tegra210 has 6 generic I2C controllers. These controllers are very58 similar to those found on Tegra124.59 items:60 - const: nvidia,tegra210-i2c61 - const: nvidia,tegra124-i2c62 - description: |63 Tegra210 has one I2C controller that is on host1x bus and is part of64 the VE power domain and typically used for camera use-cases. This VI65 I2C controller is mostly compatible with the programming model of66 the regular I2C controllers with a few exceptions. The I2C registers67 start at an offset of 0xc00 (instead of 0), registers are 16 bytes68 apart (rather than 4) and the controller does not support slave69 mode.70 const: nvidia,tegra210-i2c-vi71 - description: |72 Tegra186 has 9 generic I2C controllers, two of which are in the AON73 (always-on) partition of the SoC. All of these controllers are very74 similar to those found on Tegra210.75 const: nvidia,tegra186-i2c76 - description: |77 Tegra194 has 8 generic I2C controllers, two of which are in the AON78 (always-on) partition of the SoC. All of these controllers are very79 similar to those found on Tegra186. However, these controllers have80 support for 64 KiB transactions whereas earlier chips supported no81 more than 4 KiB per transactions.82 const: nvidia,tegra194-i2c83 84 reg:85 maxItems: 186 87 interrupts:88 maxItems: 189 90 clocks:91 minItems: 192 maxItems: 293 94 clock-names:95 minItems: 196 maxItems: 297 98 resets:99 items:100 - description: module reset101 102 reset-names:103 items:104 - const: i2c105 106 power-domains:107 maxItems: 1108 109 dmas:110 items:111 - description: DMA channel for the reception FIFO112 - description: DMA channel for the transmission FIFO113 114 dma-names:115 items:116 - const: rx117 - const: tx118 119allOf:120 - $ref: /schemas/i2c/i2c-controller.yaml121 - if:122 properties:123 compatible:124 contains:125 enum:126 - nvidia,tegra20-i2c127 - nvidia,tegra30-i2c128 then:129 properties:130 clocks:131 minItems: 2132 clock-names:133 items:134 - const: div-clk135 - const: fast-clk136 137 - if:138 properties:139 compatible:140 contains:141 enum:142 - nvidia,tegra114-i2c143 - nvidia,tegra210-i2c144 then:145 properties:146 clocks:147 maxItems: 1148 clock-names:149 items:150 - const: div-clk151 152 - if:153 properties:154 compatible:155 contains:156 const: nvidia,tegra210-i2c-vi157 then:158 properties:159 clocks:160 minItems: 2161 clock-names:162 items:163 - const: div-clk164 - const: slow165 power-domains:166 items:167 - description: phandle to the VENC power domain168 else:169 properties:170 power-domains: false171 172unevaluatedProperties: false173 174examples:175 - |176 i2c@7000c000 {177 compatible = "nvidia,tegra20-i2c";178 reg = <0x7000c000 0x100>;179 interrupts = <0 38 0x04>;180 clocks = <&tegra_car 12>, <&tegra_car 124>;181 clock-names = "div-clk", "fast-clk";182 resets = <&tegra_car 12>;183 reset-names = "i2c";184 dmas = <&apbdma 16>, <&apbdma 16>;185 dma-names = "rx", "tx";186 187 #address-cells = <1>;188 #size-cells = <0>;189 };190