90 lines · yaml
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Universal Peripheral (QUP) I2C controller8 9maintainers:10 - Andy Gross <agross@kernel.org>11 - Bjorn Andersson <bjorn.andersson@linaro.org>12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>13 14allOf:15 - $ref: /schemas/i2c/i2c-controller.yaml#16 17properties:18 compatible:19 enum:20 - qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 806421 - qcom,i2c-qup-v2.1.1 # for 8974 v122 - qcom,i2c-qup-v2.2.1 # for 8974 v2 and later23 24 clocks:25 maxItems: 226 27 clock-names:28 items:29 - const: core30 - const: iface31 32 clock-frequency:33 default: 10000034 35 dmas:36 maxItems: 237 38 dma-names:39 items:40 - const: tx41 - const: rx42 43 interrupts:44 maxItems: 145 46 pinctrl-0: true47 pinctrl-1: true48 49 pinctrl-names:50 minItems: 151 items:52 - const: default53 - const: sleep54 55 reg:56 maxItems: 157 58required:59 - compatible60 - clock-names61 - clocks62 - interrupts63 - reg64 65unevaluatedProperties: false66 67examples:68 - |69 #include <dt-bindings/clock/qcom,gcc-msm8998.h>70 #include <dt-bindings/interrupt-controller/arm-gic.h>71 72 i2c@c175000 {73 compatible = "qcom,i2c-qup-v2.2.1";74 reg = <0x0c175000 0x600>;75 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;76 77 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,78 <&gcc GCC_BLSP1_AHB_CLK>;79 clock-names = "core", "iface";80 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;81 dma-names = "tx", "rx";82 pinctrl-names = "default", "sleep";83 pinctrl-0 = <&blsp1_i2c1_default>;84 pinctrl-1 = <&blsp1_i2c1_sleep>;85 clock-frequency = <400000>;86 87 #address-cells = <1>;88 #size-cells = <0>;89 };90