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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas R-Car I2C Controller8 9maintainers:10 - Wolfram Sang <wsa+renesas@sang-engineering.com>11 12properties:13 compatible:14 oneOf:15 - items:16 - enum:17 - renesas,i2c-r8a7778 # R-Car M1A18 - renesas,i2c-r8a7779 # R-Car H119 - const: renesas,rcar-gen1-i2c # R-Car Gen120 21 - items:22 - enum:23 - renesas,i2c-r8a7742 # RZ/G1H24 - renesas,i2c-r8a7743 # RZ/G1M25 - renesas,i2c-r8a7744 # RZ/G1N26 - renesas,i2c-r8a7745 # RZ/G1E27 - renesas,i2c-r8a77470 # RZ/G1C28 - renesas,i2c-r8a7790 # R-Car H229 - renesas,i2c-r8a7791 # R-Car M2-W30 - renesas,i2c-r8a7792 # R-Car V2H31 - renesas,i2c-r8a7793 # R-Car M2-N32 - renesas,i2c-r8a7794 # R-Car E233 - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G134 35 - items:36 - enum:37 - renesas,i2c-r8a774a1 # RZ/G2M38 - renesas,i2c-r8a774b1 # RZ/G2N39 - renesas,i2c-r8a774c0 # RZ/G2E40 - renesas,i2c-r8a774e1 # RZ/G2H41 - renesas,i2c-r8a7795 # R-Car H342 - renesas,i2c-r8a7796 # R-Car M3-W43 - renesas,i2c-r8a77961 # R-Car M3-W+44 - renesas,i2c-r8a77965 # R-Car M3-N45 - renesas,i2c-r8a77970 # R-Car V3M46 - renesas,i2c-r8a77980 # R-Car V3H47 - renesas,i2c-r8a77990 # R-Car E348 - renesas,i2c-r8a77995 # R-Car D349 - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G250 51 - items:52 - enum:53 - renesas,i2c-r8a779a0 # R-Car V3U54 - renesas,i2c-r8a779f0 # R-Car S4-855 - renesas,i2c-r8a779g0 # R-Car V4H56 - renesas,i2c-r8a779h0 # R-Car V4M57 - const: renesas,rcar-gen4-i2c # R-Car Gen458 59 reg:60 maxItems: 161 62 interrupts:63 maxItems: 164 65 clock-frequency:66 description:67 Desired I2C bus clock frequency in Hz. The absence of this property68 indicates the default frequency 100 kHz.69 70 clocks:71 maxItems: 172 73 power-domains:74 maxItems: 175 76 resets:77 maxItems: 178 79 dmas:80 minItems: 281 maxItems: 482 description:83 Must contain a list of pairs of references to DMA specifiers, one for84 transmission, and one for reception.85 86 dma-names:87 minItems: 288 maxItems: 489 items:90 enum:91 - tx92 - rx93 94 i2c-scl-falling-time-ns:95 default: 3596 description:97 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C98 specification.99 100 i2c-scl-internal-delay-ns:101 default: 50102 description:103 Number of nanoseconds the IP core additionally needs to setup SCL.104 105 i2c-scl-rising-time-ns:106 default: 200107 description:108 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C109 specification.110 111required:112 - compatible113 - reg114 - interrupts115 - clocks116 - power-domains117 - '#address-cells'118 - '#size-cells'119 120allOf:121 - $ref: /schemas/i2c/i2c-controller.yaml#122 123 - if:124 properties:125 compatible:126 contains:127 enum:128 - renesas,rcar-gen1-i2c129 - renesas,rcar-gen2-i2c130 then:131 properties:132 dmas: false133 dma-names: false134 135 - if:136 properties:137 compatible:138 contains:139 enum:140 - renesas,rcar-gen2-i2c141 - renesas,rcar-gen3-i2c142 - renesas,rcar-gen4-i2c143 then:144 required:145 - resets146 147unevaluatedProperties: false148 149examples:150 - |151 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>152 #include <dt-bindings/interrupt-controller/arm-gic.h>153 #include <dt-bindings/power/r8a7791-sysc.h>154 155 i2c0: i2c@e6508000 {156 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";157 reg = <0xe6508000 0x40>;158 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;159 clock-frequency = <400000>;160 clocks = <&cpg CPG_MOD 931>;161 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;162 resets = <&cpg 931>;163 i2c-scl-internal-delay-ns = <6>;164 #address-cells = <1>;165 #size-cells = <0>;166 };167