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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2019 Analog Devices Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/iio/adc/adi,ad7192.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Analog Devices AD7192 ADC device driver9 10maintainers:11 - Michael Hennerich <michael.hennerich@analog.com>12 13description: |14 Bindings for the Analog Devices AD7192 ADC device. Datasheet can be15 found here:16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf17 18properties:19 compatible:20 enum:21 - adi,ad719022 - adi,ad719223 - adi,ad719324 - adi,ad719425 - adi,ad719526 27 "#address-cells":28 const: 129 30 "#size-cells":31 const: 032 33 reg:34 maxItems: 135 36 spi-cpol: true37 38 spi-cpha: true39 40 clocks:41 maxItems: 142 description:43 Optionally, either a crystal can be attached externally between MCLK1 and44 MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK245 pin. If absent, internal 4.92MHz clock is used, which can be made46 available on MCLK2 pin.47 48 clock-names:49 enum:50 - xtal51 - mclk52 53 "#clock-cells":54 const: 055 description:56 If present when internal clock is used, configured as clock provider.57 58 interrupts:59 maxItems: 160 61 aincom-supply:62 description: |63 AINCOM voltage supply. Analog inputs AINx are referenced to this input64 when configured for pseudo-differential operation.65 66 dvdd-supply:67 description: DVdd voltage supply68 69 avdd-supply:70 description: AVdd voltage supply71 72 vref-supply:73 description: VRef voltage supply74 75 adi,rejection-60-Hz-enable:76 description: |77 This bit enables a notch at 60 Hz when the first notch of the sinc78 filter is at 50 Hz. When REJ60 is set, a filter notch is placed at79 60 Hz when the sinc filter first notch is at 50 Hz. This allows80 simultaneous 50 Hz/ 60 Hz rejection.81 type: boolean82 83 adi,refin2-pins-enable:84 description: |85 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.86 type: boolean87 88 adi,buffer-enable:89 description: |90 Enables the buffer on the analog inputs. If cleared, the analog inputs91 are unbuffered, lowering the power consumption of the device. If this92 bit is set, the analog inputs are buffered, allowing the user to place93 source impedances on the front end without contributing gain errors to94 the system.95 type: boolean96 97 adi,burnout-currents-enable:98 description: |99 When this bit is set to 1, the 500 nA current sources in the signal100 path are enabled. When BURN = 0, the burnout currents are disabled.101 The burnout currents can be enabled only when the buffer is active102 and when chop is disabled.103 type: boolean104 105 bipolar:106 description: see Documentation/devicetree/bindings/iio/adc/adc.yaml107 type: boolean108 109patternProperties:110 "^channel@[0-9a-f]+$":111 type: object112 $ref: adc.yaml113 unevaluatedProperties: false114 115 properties:116 reg:117 description: The channel index.118 minimum: 0119 maximum: 271120 121 diff-channels:122 description:123 Both inputs can be connected to pins AIN1 to AIN16 by choosing the124 appropriate value from 1 to 16.125 items:126 minimum: 1127 maximum: 16128 129 single-channel:130 description:131 Positive input can be connected to pins AIN1 to AIN16 by choosing the132 appropriate value from 1 to 16. Negative input is connected to AINCOM.133 minimum: 1134 maximum: 16135 136 oneOf:137 - required:138 - reg139 - diff-channels140 - required:141 - reg142 - single-channel143 144required:145 - compatible146 - reg147 - interrupts148 - dvdd-supply149 - avdd-supply150 - vref-supply151 - spi-cpol152 - spi-cpha153 154allOf:155 - $ref: /schemas/spi/spi-peripheral-props.yaml#156 - if:157 properties:158 compatible:159 enum:160 - adi,ad7190161 - adi,ad7192162 - adi,ad7193163 - adi,ad7195164 then:165 patternProperties:166 "^channel@[0-9a-f]+$": false167 - if:168 anyOf:169 - required:170 - clocks171 - required:172 - clock-names173 then:174 properties:175 "#clock-cells": false176 required:177 - clocks178 - clock-names179 180unevaluatedProperties: false181 182examples:183 - |184 spi {185 #address-cells = <1>;186 #size-cells = <0>;187 188 adc@0 {189 compatible = "adi,ad7192";190 reg = <0>;191 spi-max-frequency = <1000000>;192 spi-cpol;193 spi-cpha;194 clocks = <&ad7192_mclk>;195 clock-names = "mclk";196 interrupts = <25 0x2>;197 interrupt-parent = <&gpio>;198 aincom-supply = <&aincom>;199 dvdd-supply = <&dvdd>;200 avdd-supply = <&avdd>;201 vref-supply = <&vref>;202 203 adi,refin2-pins-enable;204 adi,rejection-60-Hz-enable;205 adi,buffer-enable;206 adi,burnout-currents-enable;207 };208 };209 - |210 spi {211 #address-cells = <1>;212 #size-cells = <0>;213 214 adc@0 {215 compatible = "adi,ad7194";216 reg = <0>;217 218 #address-cells = <1>;219 #size-cells = <0>;220 221 spi-max-frequency = <1000000>;222 spi-cpol;223 spi-cpha;224 #clock-cells = <0>;225 interrupts = <25 0x2>;226 interrupt-parent = <&gpio>;227 aincom-supply = <&aincom>;228 dvdd-supply = <&dvdd>;229 avdd-supply = <&avdd>;230 vref-supply = <&vref>;231 232 channel@0 {233 reg = <0>;234 diff-channels = <1 6>;235 };236 237 channel@1 {238 reg = <1>;239 single-channel = <1>;240 };241 };242 };243