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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Analog Devices AXI ADC IP core8 9maintainers:10 - Michael Hennerich <michael.hennerich@analog.com>11 12description: |13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device14 with a high speed serial (JESD204B/C) or source synchronous parallel15 interface (LVDS/CMOS).16 Usually, some other interface type (i.e SPI) is used as a control17 interface for the actual ADC, while this IP core will interface18 to the data-lines of the ADC and handle the streaming of data into19 memory via DMA.20 21 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip22 23properties:24 compatible:25 enum:26 - adi,axi-adc-10.0.a27 28 reg:29 maxItems: 130 31 clocks:32 maxItems: 133 34 dmas:35 maxItems: 136 37 dma-names:38 items:39 - const: rx40 41 adi,adc-dev:42 $ref: /schemas/types.yaml#/definitions/phandle43 description:44 A reference to a the actual ADC to which this FPGA ADC interfaces to.45 deprecated: true46 47 '#io-backend-cells':48 const: 049 50required:51 - compatible52 - dmas53 - reg54 - clocks55 56additionalProperties: false57 58examples:59 - |60 axi-adc@44a00000 {61 compatible = "adi,axi-adc-10.0.a";62 reg = <0x44a00000 0x10000>;63 dmas = <&rx_dma 0>;64 dma-names = "rx";65 clocks = <&axi_clk>;66 #io-backend-cells = <0>;67 };68...69