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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ADC found on Freescale vf610 and similar SoCs8 9maintainers:10  - Haibo Chen <haibo.chen@nxp.com>11 12description:13  ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.14 15properties:16  compatible:17    oneOf:18      - items:19          - enum:20              - fsl,imx6sx-adc21              - fsl,imx6ul-adc22          - const: fsl,vf610-adc23      - items:24          - const: fsl,vf610-adc25 26  reg:27    maxItems: 128 29  interrupts:30    maxItems: 131 32  clocks:33    description: ADC source clock (ipg clock)34    maxItems: 135 36  clock-names:37    const: adc38 39  vref-supply:40    description: ADC reference voltage supply.41 42  fsl,adck-max-frequency:43    $ref: /schemas/types.yaml#/definitions/uint32-array44    minItems: 345    maxItems: 346    description: |47      Maximum frequencies from datasheet operating requirements.48      Three values necessary to cover the 3 conversion modes.49      * Frequency in normal mode (ADLPC=0, ADHSC=0)50      * Frequency in high-speed mode (ADLPC=0, ADHSC=1)51      * Frequency in low-power mode (ADLPC=1, ADHSC=0)52 53  min-sample-time:54    $ref: /schemas/types.yaml#/definitions/uint3255    description:56      Minimum sampling time in nanoseconds. This value has57      to be chosen according to the conversion mode and the connected analog58      source resistance (R_as) and capacitance (C_as). Refer the datasheet's59      operating requirements. A safe default across a wide range of R_as and60      C_as as well as conversion modes is 1000ns.61 62  "#io-channel-cells":63    const: 164 65required:66  - compatible67  - reg68  - interrupts69  - clocks70  - clock-names71  - vref-supply72 73additionalProperties: false74 75examples:76  - |77    #include <dt-bindings/clock/vf610-clock.h>78    adc@4003b000 {79        compatible = "fsl,vf610-adc";80        reg = <0x4003b000 0x1000>;81        interrupts = <0 53 0x04>;82        clocks = <&clks VF610_CLK_ADC0>;83        clock-names = "adc";84        fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;85        vref-supply = <&reg_vcc_3v3_mcu>;86        min-sample-time = <10000>;87    };88...89