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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/G2L ADC8 9maintainers:10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>11 12description: |13 A/D Converter block is a successive approximation analog-to-digital converter14 with a 12-bit accuracy. Up to eight analog input channels can be selected.15 Conversions can be performed in single or repeat mode. Result of the ADC is16 stored in a 32-bit data register corresponding to each channel.17 18properties:19 compatible:20 items:21 - enum:22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five23 - renesas,r9a07g044-adc # RZ/G2L24 - renesas,r9a07g054-adc # RZ/V2L25 - const: renesas,rzg2l-adc26 27 reg:28 maxItems: 129 30 interrupts:31 maxItems: 132 33 clocks:34 items:35 - description: converter clock36 - description: peripheral clock37 38 clock-names:39 items:40 - const: adclk41 - const: pclk42 43 power-domains:44 maxItems: 145 46 resets:47 maxItems: 248 49 reset-names:50 items:51 - const: presetn52 - const: adrst-n53 54 '#address-cells':55 const: 156 57 '#size-cells':58 const: 059 60required:61 - compatible62 - reg63 - interrupts64 - clocks65 - clock-names66 - power-domains67 - resets68 - reset-names69 70patternProperties:71 "^channel@[0-7]$":72 $ref: adc.yaml73 type: object74 description: |75 Represents the external channels which are connected to the ADC.76 77 properties:78 reg:79 description: |80 The channel number.81 82 required:83 - reg84 85 additionalProperties: false86 87allOf:88 - if:89 properties:90 compatible:91 contains:92 const: renesas,r9a07g043-adc93 then:94 patternProperties:95 "^channel@[2-7]$": false96 "^channel@[0-1]$":97 properties:98 reg:99 minimum: 0100 maximum: 1101 else:102 patternProperties:103 "^channel@[0-7]$":104 properties:105 reg:106 minimum: 0107 maximum: 7108 109additionalProperties: false110 111examples:112 - |113 #include <dt-bindings/clock/r9a07g044-cpg.h>114 #include <dt-bindings/interrupt-controller/arm-gic.h>115 116 adc: adc@10059000 {117 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";118 reg = <0x10059000 0x400>;119 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;120 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,121 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;122 clock-names = "adclk", "pclk";123 power-domains = <&cpg>;124 resets = <&cpg R9A07G044_ADC_PRESETN>,125 <&cpg R9A07G044_ADC_ADRST_N>;126 reset-names = "presetn", "adrst-n";127 128 #address-cells = <1>;129 #size-cells = <0>;130 131 channel@0 {132 reg = <0>;133 };134 channel@1 {135 reg = <1>;136 };137 channel@2 {138 reg = <2>;139 };140 channel@3 {141 reg = <3>;142 };143 channel@4 {144 reg = <4>;145 };146 channel@5 {147 reg = <5>;148 };149 channel@6 {150 reg = <6>;151 };152 channel@7 {153 reg = <7>;154 };155 };156