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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STM32 ADC8 9description: |10 STM32 ADC is a successive approximation analog-to-digital converter.11 It has several multiplexed input channels. Conversions can be performed12 in single, continuous, scan or discontinuous mode. Result of the ADC is13 stored in a left-aligned or right-aligned 32-bit data register.14 Conversions can be launched in software or using hardware triggers.15 16 The analog watchdog feature allows the application to detect if the input17 voltage goes beyond the user-defined, higher or lower thresholds.18 19 Each STM32 ADC block can have up to 3 ADC instances.20 21maintainers:22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>23 24properties:25 compatible:26 enum:27 - st,stm32f4-adc-core28 - st,stm32h7-adc-core29 - st,stm32mp1-adc-core30 - st,stm32mp13-adc-core31 32 reg:33 maxItems: 134 35 interrupts:36 description: |37 One or more interrupts for ADC block, depending on part used:38 - stm32f4 and stm32h7 share a common ADC interrupt line.39 - stm32mp1 has two separate interrupt lines, one for each ADC within40 ADC block.41 - stm32mp13 has an interrupt line per ADC block.42 minItems: 143 maxItems: 244 45 clocks:46 minItems: 147 maxItems: 248 description: |49 Core can use up to two clocks, depending on part used:50 - "adc" clock: for the analog circuitry, common to all ADCs.51 It's required on stm32f4.52 It's optional on stm32h7 and stm32mp1.53 - "bus" clock: for registers access, common to all ADCs.54 It's not present on stm32f4.55 It's required on stm32h7 and stm32mp1.56 57 clock-names:58 minItems: 159 maxItems: 260 61 st,max-clk-rate-hz:62 description:63 Allow to specify desired max clock rate used by analog circuitry.64 65 vdda-supply:66 description: Phandle to the vdda input analog voltage.67 68 vref-supply:69 description: Phandle to the vref input analog reference voltage.70 71 booster-supply:72 description:73 Phandle to the embedded booster regulator that can be used to supply ADC74 analog input switches on stm32h7 and stm32mp1.75 76 vdd-supply:77 description:78 Phandle to the vdd input voltage. It can be used to supply ADC analog79 input switches on stm32mp1.80 81 st,syscfg:82 description:83 Phandle to system configuration controller. It can be used to control the84 analog circuitry on stm32mp1.85 $ref: /schemas/types.yaml#/definitions/phandle-array86 87 interrupt-controller: true88 89 '#interrupt-cells':90 const: 191 92 '#address-cells':93 const: 194 95 '#size-cells':96 const: 097 98 access-controllers:99 minItems: 1100 maxItems: 2101 102allOf:103 - if:104 properties:105 compatible:106 contains:107 const: st,stm32f4-adc-core108 109 then:110 properties:111 clocks:112 maxItems: 1113 114 clock-names:115 const: adc116 117 interrupts:118 items:119 - description: interrupt line common for all ADCs120 121 st,max-clk-rate-hz:122 minimum: 600000123 maximum: 36000000124 default: 36000000125 126 booster-supply: false127 128 vdd-supply: false129 130 st,syscfg: false131 132 - if:133 properties:134 compatible:135 contains:136 const: st,stm32h7-adc-core137 138 then:139 properties:140 clocks:141 minItems: 1142 maxItems: 2143 144 clock-names:145 items:146 - const: bus147 - const: adc148 minItems: 1149 150 interrupts:151 items:152 - description: interrupt line common for all ADCs153 154 st,max-clk-rate-hz:155 minimum: 120000156 maximum: 36000000157 default: 36000000158 159 vdd-supply: false160 161 st,syscfg: false162 163 - if:164 properties:165 compatible:166 contains:167 const: st,stm32mp1-adc-core168 169 then:170 properties:171 clocks:172 minItems: 1173 maxItems: 2174 175 clock-names:176 items:177 - const: bus178 - const: adc179 minItems: 1180 181 interrupts:182 items:183 - description: interrupt line for ADC1184 - description: interrupt line for ADC2185 186 st,max-clk-rate-hz:187 minimum: 120000188 maximum: 36000000189 default: 36000000190 191 - if:192 properties:193 compatible:194 contains:195 const: st,stm32mp13-adc-core196 197 then:198 properties:199 clocks:200 minItems: 1201 maxItems: 2202 203 clock-names:204 items:205 - const: bus206 - const: adc207 minItems: 1208 209 interrupts:210 items:211 - description: ADC interrupt line212 213 st,max-clk-rate-hz:214 minimum: 150000215 maximum: 75000000216 default: 75000000217 218additionalProperties: false219 220required:221 - compatible222 - reg223 - interrupts224 - clocks225 - clock-names226 - vdda-supply227 - vref-supply228 - interrupt-controller229 - '#interrupt-cells'230 - '#address-cells'231 - '#size-cells'232 233patternProperties:234 "^adc@[0-9]+$":235 type: object236 description:237 An ADC block node should contain at least one subnode, representing an238 ADC instance available on the machine.239 240 properties:241 compatible:242 enum:243 - st,stm32f4-adc244 - st,stm32h7-adc245 - st,stm32mp1-adc246 - st,stm32mp13-adc247 248 reg:249 description: |250 Offset of ADC instance in ADC block. Valid values are:251 - 0x0: ADC1252 - 0x100: ADC2253 - 0x200: ADC3 (stm32f4 only)254 maxItems: 1255 256 '#io-channel-cells':257 const: 1258 259 '#address-cells':260 const: 1261 262 '#size-cells':263 const: 0264 265 interrupts:266 description: |267 IRQ Line for the ADC instance. Valid values are:268 - 0 for adc@0 (single adc for stm32mp13)269 - 1 for adc@100270 - 2 for adc@200 (stm32f4 only)271 maxItems: 1272 273 clocks:274 description:275 Input clock private to this ADC instance. It's required only on276 stm32f4, that has per instance clock input for registers access.277 maxItems: 1278 279 dmas:280 description: RX DMA Channel281 maxItems: 1282 283 dma-names:284 const: rx285 286 assigned-resolution-bits:287 description: |288 Resolution (bits) to use for conversions:289 - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13290 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1291 292 st,adc-channels:293 description: |294 List of single-ended channels muxed for this ADC. It can have up to:295 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4296 - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.297 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and298 stm32mp1.299 $ref: /schemas/types.yaml#/definitions/uint32-array300 deprecated: true301 302 st,adc-diff-channels:303 description: |304 List of differential channels muxed for this ADC. Some channels can305 be configured as differential instead of single-ended on stm32h7 and306 on stm32mp1. Positive and negative inputs pairs are listed:307 <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.308 309 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is310 required if no adc generic channel is defined. These legacy channel311 properties are exclusive with adc generic channel bindings.312 Both properties can be used together. Some channels can be313 used as single-ended and some other ones as differential (mixed). But314 channels can't be configured both as single-ended and differential.315 $ref: /schemas/types.yaml#/definitions/uint32-matrix316 items:317 items:318 - description: |319 "vinp" indicates positive input number320 minimum: 0321 maximum: 19322 - description: |323 "vinn" indicates negative input number324 minimum: 0325 maximum: 19326 deprecated: true327 328 st,min-sample-time-nsecs:329 description:330 Minimum sampling time in nanoseconds. Depending on hardware (board)331 e.g. high/low analog input source impedance, fine tune of ADC332 sampling time may be recommended. This can be either one value or an333 array that matches "st,adc-channels" and/or "st,adc-diff-channels"334 list, to set sample time resp. for all channels, or independently for335 each channel.336 $ref: /schemas/types.yaml#/definitions/uint32-array337 deprecated: true338 339 nvmem-cells:340 items:341 - description: Phandle to the calibration vrefint data provided by otp342 343 nvmem-cell-names:344 items:345 - const: vrefint346 347 patternProperties:348 "^channel@([0-9]|1[0-9])$":349 type: object350 $ref: adc.yaml351 description: Represents the external channels which are connected to the ADC.352 353 properties:354 reg:355 items:356 minimum: 0357 maximum: 19358 359 label:360 description: |361 Unique name to identify which channel this is.362 Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"363 are used to identify internal channels with matching names.364 365 diff-channels:366 $ref: /schemas/types.yaml#/definitions/uint32-array367 items:368 minimum: 0369 maximum: 19370 371 st,min-sample-time-ns:372 description: |373 Minimum sampling time in nanoseconds. Depending on hardware (board)374 e.g. high/low analog input source impedance, fine tune of ADC375 sampling time may be recommended.376 377 required:378 - reg379 380 additionalProperties: false381 382 allOf:383 - if:384 properties:385 compatible:386 contains:387 const: st,stm32f4-adc388 389 then:390 properties:391 reg:392 enum:393 - 0x0394 - 0x100395 - 0x200396 397 interrupts:398 minimum: 0399 maximum: 2400 401 assigned-resolution-bits:402 enum: [6, 8, 10, 12]403 default: 12404 405 st,adc-channels:406 minItems: 1407 maxItems: 16408 items:409 minimum: 0410 maximum: 15411 412 st,adc-diff-channels: false413 414 st,min-sample-time-nsecs:415 minItems: 1416 maxItems: 16417 items:418 minimum: 80419 420 required:421 - clocks422 423 - if:424 properties:425 compatible:426 contains:427 enum:428 - st,stm32h7-adc429 - st,stm32mp1-adc430 431 then:432 properties:433 reg:434 enum:435 - 0x0436 - 0x100437 438 interrupts:439 minimum: 0440 maximum: 1441 442 assigned-resolution-bits:443 enum: [8, 10, 12, 14, 16]444 default: 16445 446 st,adc-channels:447 minItems: 1448 maxItems: 20449 items:450 minimum: 0451 maximum: 19452 453 st,min-sample-time-nsecs:454 minItems: 1455 maxItems: 20456 items:457 minimum: 40458 459 460 - if:461 properties:462 compatible:463 contains:464 const: st,stm32mp13-adc465 466 then:467 properties:468 reg:469 const: 0x0470 471 interrupts:472 const: 0473 474 assigned-resolution-bits:475 enum: [6, 8, 10, 12]476 default: 12477 478 st,adc-channels:479 minItems: 1480 maxItems: 19481 items:482 minimum: 0483 maximum: 18484 485 st,min-sample-time-nsecs:486 minItems: 1487 maxItems: 19488 items:489 minimum: 40490 additionalProperties: false491 492 required:493 - compatible494 - reg495 - interrupts496 - '#io-channel-cells'497 498examples:499 - |500 // Example 1: with stm32f429, ADC1, single-ended channel 8501 adc123: adc@40012000 {502 compatible = "st,stm32f4-adc-core";503 reg = <0x40012000 0x400>;504 interrupts = <18>;505 clocks = <&rcc 0 168>;506 clock-names = "adc";507 st,max-clk-rate-hz = <36000000>;508 vdda-supply = <&vdda>;509 vref-supply = <&vref>;510 interrupt-controller;511 #interrupt-cells = <1>;512 #address-cells = <1>;513 #size-cells = <0>;514 adc@0 {515 compatible = "st,stm32f4-adc";516 #io-channel-cells = <1>;517 reg = <0x0>;518 clocks = <&rcc 0 168>;519 interrupt-parent = <&adc123>;520 interrupts = <0>;521 st,adc-channels = <8>;522 dmas = <&dma2 0 0 0x400 0x0>;523 dma-names = "rx";524 assigned-resolution-bits = <8>;525 };526 // ...527 // other adc child nodes follow...528 };529 530 - |531 // Example 2: with stm32mp157c to setup ADC1 with:532 // - channels 0 & 1 as single-ended533 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)534 #include <dt-bindings/interrupt-controller/arm-gic.h>535 #include <dt-bindings/clock/stm32mp1-clks.h>536 adc12: adc@48003000 {537 compatible = "st,stm32mp1-adc-core";538 reg = <0x48003000 0x400>;539 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,540 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;541 clocks = <&rcc ADC12>, <&rcc ADC12_K>;542 clock-names = "bus", "adc";543 booster-supply = <&booster>;544 vdd-supply = <&vdd>;545 vdda-supply = <&vdda>;546 vref-supply = <&vref>;547 st,syscfg = <&syscfg>;548 interrupt-controller;549 #interrupt-cells = <1>;550 #address-cells = <1>;551 #size-cells = <0>;552 adc@0 {553 compatible = "st,stm32mp1-adc";554 #io-channel-cells = <1>;555 reg = <0x0>;556 interrupt-parent = <&adc12>;557 interrupts = <0>;558 st,adc-channels = <0 1>;559 st,adc-diff-channels = <2 6>, <3 7>;560 st,min-sample-time-nsecs = <5000>;561 dmas = <&dmamux1 9 0x400 0x05>;562 dma-names = "rx";563 };564 // ...565 // other adc child node follow...566 };567 568 - |569 // Example 3: with stm32mp157c to setup ADC2 with:570 // - internal channels 13, 14, 15.571 #include <dt-bindings/interrupt-controller/arm-gic.h>572 #include <dt-bindings/clock/stm32mp1-clks.h>573 adc122: adc@48003000 {574 compatible = "st,stm32mp1-adc-core";575 reg = <0x48003000 0x400>;576 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,577 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;578 clocks = <&rcc ADC12>, <&rcc ADC12_K>;579 clock-names = "bus", "adc";580 booster-supply = <&booster>;581 vdd-supply = <&vdd>;582 vdda-supply = <&vdda>;583 vref-supply = <&vref>;584 st,syscfg = <&syscfg>;585 interrupt-controller;586 #interrupt-cells = <1>;587 #address-cells = <1>;588 #size-cells = <0>;589 adc@100 {590 compatible = "st,stm32mp1-adc";591 #io-channel-cells = <1>;592 reg = <0x100>;593 interrupts = <1>;594 #address-cells = <1>;595 #size-cells = <0>;596 channel@13 {597 reg = <13>;598 label = "vrefint";599 st,min-sample-time-ns = <9000>;600 };601 channel@14 {602 reg = <14>;603 label = "vddcore";604 st,min-sample-time-ns = <9000>;605 };606 channel@15 {607 reg = <15>;608 label = "vbat";609 st,min-sample-time-ns = <9000>;610 };611 };612 };613 614...615