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1Xilinx XADC device driver2 3This binding document describes the bindings for the Xilinx 7 Series XADC as well4as the UltraScale/UltraScale+ System Monitor.5 6The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.7The XADC has a DRP interface for communication. Currently two different8frontends for the DRP interface exist. One that is only available on the ZYNQ9family as a hardmacro in the SoC portion of the ZYNQ. The other one is available10on all series 7 platforms and is a softmacro with a AXI interface. This binding11document describes the bindings for both of them since the bindings are very12similar.13 14The Xilinx System Monitor is an ADC that is found in the UltraScale and15UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for16communication. Xilinx provides a standard IP core that can be used to access the17System Monitor through an AXI interface in the FPGA fabric. This IP core is18called the Xilinx System Management Wizard. This document describes the bindings19for this IP.20 21Required properties:22 - compatible: Should be one of23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device24 configuration interface to interface to the XADC hardmacro.25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to26 interface to the XADC hardmacro.27 * "xlnx,system-management-wiz-1.3": When using the28 Xilinx System Management Wizard fabric IP core to access the29 UltraScale and UltraScale+ System Monitor.30 - reg: Address and length of the register set for the device31 - interrupts: Interrupt for the XADC control interface.32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,33 when using the axi-xadc or the axi-system-management-wizard this must be34 the clock that provides the clock to the AXI bus interface of the core.35 36Optional properties:37 - xlnx,external-mux:38 * "none": No external multiplexer is used, this is the default39 if the property is omitted.40 * "single": External multiplexer mode is used with one41 multiplexer.42 * "dual": External multiplexer mode is used with two43 multiplexers for simultaneous sampling.44 - xlnx,external-mux-channel: Configures which pair of pins is used to45 sample data in external mux mode.46 Valid values for single external multiplexer mode are:47 0: VP/VN48 1: VAUXP[0]/VAUXN[0]49 2: VAUXP[1]/VAUXN[1]50 ...51 16: VAUXP[15]/VAUXN[15]52 Valid values for dual external multiplexer mode are:53 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]54 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]55 ...56 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]57 58 This property needs to be present if the device is configured for59 external multiplexer mode (either single or dual). If the device is60 not using external multiplexer mode the property is ignored.61 - xnlx,channels: List of external channels that are connected to the ADC62 Required properties:63 * #address-cells: Should be 1.64 * #size-cells: Should be 0.65 66 The child nodes of this node represent the external channels which are67 connected to the ADC. If the property is no present no external68 channels will be assumed to be connected.69 70 Each child node represents one channel and has the following71 properties:72 Required properties:73 * reg: Pair of pins the channel is connected to.74 0: VP/VN75 1: VAUXP[0]/VAUXN[0]76 2: VAUXP[1]/VAUXN[1]77 ...78 16: VAUXP[15]/VAUXN[15]79 Note each channel number should only be used at most80 once.81 Optional properties:82 * xlnx,bipolar: If set the channel is used in bipolar83 mode.84 85 86Examples:87 xadc@f8007100 {88 compatible = "xlnx,zynq-xadc-1.00.a";89 reg = <0xf8007100 0x20>;90 interrupts = <0 7 4>;91 interrupt-parent = <&gic>;92 clocks = <&pcap_clk>;93 94 xlnx,channels {95 #address-cells = <1>;96 #size-cells = <0>;97 channel@0 {98 reg = <0>;99 };100 channel@1 {101 reg = <1>;102 };103 channel@8 {104 reg = <8>;105 };106 };107 };108 109 xadc@43200000 {110 compatible = "xlnx,axi-xadc-1.00.a";111 reg = <0x43200000 0x1000>;112 interrupts = <0 53 4>;113 interrupt-parent = <&gic>;114 clocks = <&fpga1_clk>;115 116 xlnx,channels {117 #address-cells = <1>;118 #size-cells = <0>;119 channel@0 {120 reg = <0>;121 xlnx,bipolar;122 };123 };124 };125 126 adc@80000000 {127 compatible = "xlnx,system-management-wiz-1.3";128 reg = <0x80000000 0x1000>;129 interrupts = <0 81 4>;130 interrupt-parent = <&gic>;131 clocks = <&fpga1_clk>;132 133 xlnx,channels {134 #address-cells = <1>;135 #size-cells = <0>;136 channel@0 {137 reg = <0>;138 xlnx,bipolar;139 };140 };141 };142