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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Analog Devices ADIS16480 and similar IMUs8 9maintainers:10 - Alexandru Tachici <alexandru.tachici@analog.com>11 12properties:13 compatible:14 enum:15 - adi,adis1637516 - adi,adis1648017 - adi,adis1648518 - adi,adis1648819 - adi,adis1649020 - adi,adis16495-121 - adi,adis16495-222 - adi,adis16495-323 - adi,adis16497-124 - adi,adis16497-225 - adi,adis16497-326 - adi,adis16545-127 - adi,adis16545-228 - adi,adis16545-329 - adi,adis16547-130 - adi,adis16547-231 - adi,adis16547-332 33 reg:34 maxItems: 135 36 interrupts:37 minItems: 138 maxItems: 239 description: |40 Accepted interrupt types are:41 * IRQ_TYPE_EDGE_RISING42 * IRQ_TYPE_EDGE_FALLING43 44 interrupt-names:45 minItems: 146 maxItems: 247 description:48 Default if not supplied is DIO1.49 items:50 enum:51 - DIO152 - DIO253 - DIO354 - DIO455 56 spi-cpha: true57 spi-cpol: true58 59 reset-gpios:60 maxItems: 161 description: Connected to RESET pin which is active low.62 63 clocks:64 maxItems: 165 description: If not provided, then the internal clock is used.66 67 clock-names:68 description: |69 sync: In sync mode, the internal clock is disabled and the frequency70 of the external clock signal establishes therate of data71 collection and processing. See Fig 14 and 15 in the datasheet.72 The clock-frequency must be:73 * 3000 to 4500 Hz for adis1649x devices.74 * 700 to 2400 Hz for adis1648x devices.75 pps: In Pulse Per Second (PPS) Mode, the rate of data collection and76 production is equal to the product of the external clock77 frequency and the scale factor in the SYNC_SCALE register, see78 Table 154 in the datasheet.79 The clock-frequency must be:80 * 1 to 128 Hz for adis1649x devices.81 * This mode is not supported by adis1648x devices.82 enum:83 - sync84 - pps85 86 adi,ext-clk-pin:87 $ref: /schemas/types.yaml#/definitions/string88 description: |89 The DIOx line to be used as an external clock input.90 Each DIOx pin supports only one function at a time (data ready line91 selection or external clock input). When a single pin has two92 two assignments, the enable bit for the lower priority function93 automatically resets to zero (disabling the lower priority function).94 Data ready has highest priority.95 If not provided then DIO2 is assigned as default external clock96 input pin.97 enum:98 - DIO199 - DIO2100 - DIO3101 - DIO4102 103required:104 - compatible105 - reg106 - interrupts107 - spi-cpha108 - spi-cpol109 - spi-max-frequency110 111allOf:112 - $ref: /schemas/spi/spi-peripheral-props.yaml#113 114unevaluatedProperties: false115 116examples:117 - |118 #include <dt-bindings/interrupt-controller/irq.h>119 spi {120 #address-cells = <1>;121 #size-cells = <0>;122 123 imu@0 {124 compatible = "adi,adis16495-1";125 reg = <0>;126 spi-max-frequency = <3200000>;127 spi-cpol;128 spi-cpha;129 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;130 interrupt-parent = <&gpio>;131 interrupt-names = "DIO2";132 clocks = <&adis16495_sync>;133 clock-names = "sync";134 adi,ext-clk-pin = "DIO1";135 };136 };137...138