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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Generic i.MX bus frequency device8 9maintainers:10 - Peng Fan <peng.fan@nxp.com>11 12description: |13 The i.MX SoC family has multiple buses for which clock frequency (and14 sometimes voltage) can be adjusted.15 16 Some of those buses expose register areas mentioned in the memory maps as GPV17 ("Global Programmers View") but not all. Access to this area might be denied18 for normal (non-secure) world.19 20 The buses are based on externally licensed IPs such as ARM NIC-301 and21 Arteris FlexNOC but DT bindings are specific to the integration of these bus22 interconnect IPs into imx SOCs.23 24properties:25 compatible:26 oneOf:27 - items:28 - enum:29 - fsl,imx8mm-nic30 - fsl,imx8mn-nic31 - fsl,imx8mp-nic32 - fsl,imx8mq-nic33 - const: fsl,imx8m-nic34 - items:35 - enum:36 - fsl,imx8mm-noc37 - fsl,imx8mn-noc38 - fsl,imx8mp-noc39 - fsl,imx8mq-noc40 - const: fsl,imx8m-noc41 - const: fsl,imx8m-nic42 43 reg:44 maxItems: 145 46 clocks:47 maxItems: 148 49 operating-points-v2: true50 opp-table:51 type: object52 53 fsl,ddrc:54 $ref: /schemas/types.yaml#/definitions/phandle55 description:56 Phandle to DDR Controller.57 58 '#interconnect-cells':59 description:60 If specified then also act as an interconnect provider. Should only be61 set once per soc on the main noc.62 const: 163 64required:65 - compatible66 - clocks67 68additionalProperties: false69 70examples:71 - |72 #include <dt-bindings/clock/imx8mm-clock.h>73 #include <dt-bindings/interconnect/imx8mm.h>74 #include <dt-bindings/interrupt-controller/arm-gic.h>75 76 noc: interconnect@32700000 {77 compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";78 reg = <0x32700000 0x100000>;79 clocks = <&clk IMX8MM_CLK_NOC>;80 #interconnect-cells = <1>;81 fsl,ddrc = <&ddrc>;82 83 operating-points-v2 = <&noc_opp_table>;84 noc_opp_table: opp-table {85 compatible = "operating-points-v2";86 87 opp-133333333 {88 opp-hz = /bits/ 64 <133333333>;89 };90 opp-800000000 {91 opp-hz = /bits/ 64 <800000000>;92 };93 };94 };95 96 ddrc: memory-controller@3d400000 {97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";98 reg = <0x3d400000 0x400000>;99 clock-names = "core", "pll", "alt", "apb";100 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,101 <&clk IMX8MM_DRAM_PLL>,102 <&clk IMX8MM_CLK_DRAM_ALT>,103 <&clk IMX8MM_CLK_DRAM_APB>;104 };105