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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider8 9maintainers:10 - Sibi Sankar <quic_sibis@quicinc.com>11 12description:13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests15 from CPU/GPU and relays it to the OSM.16 17properties:18 compatible:19 oneOf:20 - items:21 - enum:22 - qcom,sc7180-osm-l323 - qcom,sc8180x-osm-l324 - qcom,sdm670-osm-l325 - qcom,sdm845-osm-l326 - qcom,sm6350-osm-l327 - qcom,sm8150-osm-l328 - const: qcom,osm-l329 - items:30 - enum:31 - qcom,sc7280-epss-l332 - qcom,sc8280xp-epss-l333 - qcom,sm6375-cpucp-l334 - qcom,sm8250-epss-l335 - qcom,sm8350-epss-l336 - const: qcom,epss-l337 38 reg:39 maxItems: 140 41 clocks:42 items:43 - description: xo clock44 - description: alternate clock45 46 clock-names:47 items:48 - const: xo49 - const: alternate50 51 '#interconnect-cells':52 const: 153 54required:55 - compatible56 - reg57 - clocks58 - clock-names59 - '#interconnect-cells'60 61additionalProperties: false62 63examples:64 - |65 66 #define GPLL0 16567 #define RPMH_CXO_CLK 068 69 osm_l3: interconnect@17d41000 {70 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";71 reg = <0x17d41000 0x1400>;72 73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;74 clock-names = "xo", "alternate";75 76 #interconnect-cells = <1>;77 };78