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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Apple Interrupt Controller8 9maintainers:10 - Hector Martin <marcan@marcan.st>11 12description: |13 The Apple Interrupt Controller is a simple interrupt controller present on14 Apple ARM SoC platforms, including various iPhone and iPad devices and the15 "Apple Silicon" Macs.16 17 It provides the following features:18 19 - Level-triggered hardware IRQs wired to SoC blocks20 - Single mask bit per IRQ21 - Per-IRQ affinity setting22 - Automatic masking on event delivery (auto-ack)23 - Software triggering (ORed with hw line)24 - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable25 if not symmetric)26 - Automatic prioritization (single event/ack register per CPU, lower IRQs =27 higher priority)28 - Automatic masking on ack29 - Default "this CPU" register view and explicit per-CPU views30 31 This device also represents the FIQ interrupt sources on platforms using AIC,32 which do not go through a discrete interrupt controller.33 34 IPIs may be performed via MMIO registers on all variants of AIC. Starting35 from A11, system registers may also be used for "fast" IPIs. Starting from36 M1, even faster IPIs within the same cluster may be achieved by writing to37 a "local" fast IPI register as opposed to using the "global" fast IPI38 register.39 40allOf:41 - $ref: /schemas/interrupt-controller.yaml#42 43properties:44 compatible:45 items:46 - enum:47 - apple,s5l8960x-aic48 - apple,t7000-aic49 - apple,s8000-aic50 - apple,t8010-aic51 - apple,t8015-aic52 - apple,t8103-aic53 - const: apple,aic54 55 interrupt-controller: true56 57 '#interrupt-cells':58 const: 359 description: |60 The 1st cell contains the interrupt type:61 - 0: Hardware IRQ62 - 1: FIQ63 64 The 2nd cell contains the interrupt number.65 - HW IRQs: interrupt number66 - FIQs:67 - 0: physical HV timer68 - 1: virtual HV timer69 - 2: physical guest timer70 - 3: virtual guest timer71 - 4: 'efficient' CPU PMU72 - 5: 'performance' CPU PMU73 74 The 3rd cell contains the interrupt flags. This is normally75 IRQ_TYPE_LEVEL_HIGH (4).76 77 reg:78 description: |79 Specifies base physical address and size of the AIC registers.80 maxItems: 181 82 power-domains:83 maxItems: 184 85 affinities:86 type: object87 additionalProperties: false88 description:89 FIQ affinity can be expressed as a single "affinities" node,90 containing a set of sub-nodes, one per FIQ with a non-default91 affinity.92 patternProperties:93 "^.+-affinity$":94 type: object95 additionalProperties: false96 properties:97 apple,fiq-index:98 description:99 The interrupt number specified as a FIQ, and for which100 the affinity is not the default.101 $ref: /schemas/types.yaml#/definitions/uint32102 maximum: 5103 104 cpus:105 description:106 Should be a list of phandles to CPU nodes (as described in107 Documentation/devicetree/bindings/arm/cpus.yaml).108 109 required:110 - apple,fiq-index111 - cpus112 113required:114 - compatible115 - '#interrupt-cells'116 - interrupt-controller117 - reg118 119additionalProperties: false120 121examples:122 - |123 soc {124 #address-cells = <2>;125 #size-cells = <2>;126 127 aic: interrupt-controller@23b100000 {128 compatible = "apple,t8103-aic", "apple,aic";129 #interrupt-cells = <3>;130 interrupt-controller;131 reg = <0x2 0x3b100000 0x0 0x8000>;132 };133 };134