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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM Generic Interrupt Controller v1 and v28 9maintainers:10 - Marc Zyngier <marc.zyngier@arm.com>11 12description: |+13 ARM SMP cores are often associated with a GIC, providing per processor14 interrupts (PPI), shared processor interrupts (SPI) and software15 generated interrupts (SGI).16 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.18 Secondary GICs are cascaded into the upward interrupt controller and do not19 have PPIs or SGIs.20 21allOf:22 - $ref: /schemas/interrupt-controller.yaml#23 24properties:25 compatible:26 oneOf:27 - items:28 - enum:29 - arm,arm11mp-gic30 - arm,cortex-a15-gic31 - arm,cortex-a7-gic32 - arm,cortex-a5-gic33 - arm,cortex-a9-gic34 - arm,eb11mp-gic35 - arm,gic-40036 - arm,pl39037 - arm,tc11mp-gic38 - qcom,msm-8660-qgic39 - qcom,msm-qgic240 41 - items:42 - const: arm,gic-40043 - enum:44 - arm,cortex-a15-gic45 - arm,cortex-a7-gic46 47 - items:48 - const: arm,arm1176jzf-devchip-gic49 - const: arm,arm11mp-gic50 51 - items:52 - const: brcm,brahma-b15-gic53 - const: arm,cortex-a15-gic54 55 - oneOf:56 - const: nvidia,tegra210-agic57 - items:58 - enum:59 - nvidia,tegra186-agic60 - nvidia,tegra194-agic61 - nvidia,tegra234-agic62 - const: nvidia,tegra210-agic63 64 interrupt-controller: true65 66 "#address-cells":67 enum: [ 0, 1, 2 ]68 "#size-cells":69 enum: [ 1, 2 ]70 71 "#interrupt-cells":72 const: 373 description: |74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI75 interrupts.76 77 The 2nd cell contains the interrupt number for the interrupt type.78 SPI interrupts are in the range [0-987]. PPI interrupts are in the79 range [0-15].80 81 The 3rd cell is the flags, encoded as follows:82 bits[3:0] trigger type and level flags.83 1 = low-to-high edge triggered84 2 = high-to-low edge triggered (invalid for SPIs)85 4 = active high level-sensitive86 8 = active low level-sensitive (invalid for SPIs).87 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of88 the 8 possible cpus attached to the GIC. A bit set to '1' indicated89 the interrupt is wired to that CPU. Only valid for PPI interrupts.90 Also note that the configurability of PPI interrupts is IMPLEMENTATION91 DEFINED and as such not guaranteed to be present (most SoC available92 in 2014 seem to ignore the setting of this flag and use the hardware93 default value).94 95 reg:96 description: |97 Specifies base physical address(s) and size of the GIC registers. The98 first region is the GIC distributor register base and size. The 2nd region99 is the GIC cpu interface register base and size.100 101 For GICv2 with virtualization extensions, additional regions are102 required for specifying the base physical address and size of the VGIC103 registers. The first additional region is the GIC virtual interface104 control register base and size. The 2nd additional region is the GIC105 virtual cpu interface register base and size.106 minItems: 2107 maxItems: 4108 109 ranges: true110 111 interrupts:112 description: Interrupt source of the parent interrupt controller on113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see114 below).115 maxItems: 1116 117 cpu-offset:118 description: per-cpu offset within the distributor and cpu interface119 regions, used when the GIC doesn't have banked registers. The offset120 is cpu-offset * cpu-nr.121 $ref: /schemas/types.yaml#/definitions/uint32122 123 clocks:124 minItems: 1125 maxItems: 2126 127 clock-names:128 description: List of names for the GIC clock input(s). Valid clock names129 depend on the GIC variant.130 oneOf:131 - const: ic_clk # for "arm,arm11mp-gic"132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"133 - items: # for "arm,cortex-a9-gic"134 - const: PERIPHCLK135 - const: PERIPHCLKEN136 - const: clk # for "arm,gic-400" and "nvidia,tegra210"137 - const: gclk # for "arm,pl390"138 139 power-domains:140 maxItems: 1141 142 resets:143 maxItems: 1144 145required:146 - compatible147 - reg148 149patternProperties:150 "^v2m@[0-9a-f]+$":151 type: object152 description: |153 * GICv2m extension for MSI/MSI-x support (Optional)154 155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).156 This is enabled by specifying v2m sub-node(s).157 158 properties:159 compatible:160 const: arm,gic-v2m-frame161 162 msi-controller: true163 164 reg:165 maxItems: 1166 description: GICv2m MSI interface register base and size167 168 arm,msi-base-spi:169 description: When the MSI_TYPER register contains an incorrect value,170 this property should contain the SPI base of the MSI frame, overriding171 the HW value.172 $ref: /schemas/types.yaml#/definitions/uint32173 174 arm,msi-num-spis:175 description: When the MSI_TYPER register contains an incorrect value,176 this property should contain the number of SPIs assigned to the177 frame, overriding the HW value.178 $ref: /schemas/types.yaml#/definitions/uint32179 180 required:181 - compatible182 - msi-controller183 - reg184 185 additionalProperties: false186 187additionalProperties: false188 189examples:190 - |191 // GICv1192 intc: interrupt-controller@fff11000 {193 compatible = "arm,cortex-a9-gic";194 #interrupt-cells = <3>;195 #address-cells = <1>;196 interrupt-controller;197 reg = <0xfff11000 0x1000>,198 <0xfff10100 0x100>;199 };200 201 - |202 // GICv2203 interrupt-controller@2c001000 {204 compatible = "arm,cortex-a15-gic";205 #interrupt-cells = <3>;206 interrupt-controller;207 reg = <0x2c001000 0x1000>,208 <0x2c002000 0x2000>,209 <0x2c004000 0x2000>,210 <0x2c006000 0x2000>;211 interrupts = <1 9 0xf04>;212 };213 214 - |215 // GICv2m extension for MSI/MSI-x support216 interrupt-controller@e1101000 {217 compatible = "arm,gic-400";218 #interrupt-cells = <3>;219 #address-cells = <1>;220 #size-cells = <1>;221 interrupt-controller;222 interrupts = <1 8 0xf04>;223 ranges = <0 0xe1100000 0x100000>;224 reg = <0xe1110000 0x01000>,225 <0xe112f000 0x02000>,226 <0xe1140000 0x10000>,227 <0xe1160000 0x10000>;228 229 v2m0: v2m@80000 {230 compatible = "arm,gic-v2m-frame";231 msi-controller;232 reg = <0x80000 0x1000>;233 };234 235 //...236 237 v2mN: v2m@90000 {238 compatible = "arm,gic-v2m-frame";239 msi-controller;240 reg = <0x90000 0x1000>;241 };242 };243...244