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1* ARM Versatile FPGA interrupt controller2 3One or more FPGA IRQ controllers can be synthesized in an ARM reference board4such as the Integrator or Versatile family. The output of these different5controllers are OR:ed together and fed to the CPU tile's IRQ input. Each6instance can handle up to 32 interrupts.7 8Required properties:9- compatible: "arm,versatile-fpga-irq"10- interrupt-controller: Identifies the node as an interrupt controller11- #interrupt-cells: The number of cells to define the interrupts. Must be 112 as the FPGA IRQ controller has no configuration options for interrupt13 sources. The cell is a u32 and defines the interrupt number.14- reg: The register bank for the FPGA interrupt controller.15- clear-mask: a u32 number representing the mask written to clear all IRQs16 on the controller at boot for example.17- valid-mask: a u32 number representing a bit mask determining which of18 the interrupts are valid. Unconnected/unused lines are set to 0, and19 the system till not make it possible for devices to request these20 interrupts.21 22The "oxsemi,ox810se-rps-irq" compatible is deprecated.23 24Example:25 26pic: pic@14000000 {27 compatible = "arm,versatile-fpga-irq";28 #interrupt-cells = <1>;29 interrupt-controller;30 reg = <0x14000000 0x100>;31 clear-mask = <0xffffffff>;32 valid-mask = <0x003fffff>;33};34 35Optional properties:36- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ37 output is simply connected to the input of another IRQ controller,38 then the parent IRQ shall be specified in this property.39