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1Broadcom BCM6345-style Level 1 interrupt controller2 3This block is a first level interrupt controller that is typically connected4directly to one of the HW INT lines on each CPU.5 6Key elements of the hardware design include:7 8- 32, 64 or 128 incoming level IRQ lines9 10- Most onchip peripherals are wired directly to an L1 input11 12- A separate instance of the register set for each CPU, allowing individual13 peripheral IRQs to be routed to any CPU14 15- Contains one or more enable/status word pairs per CPU16 17- No atomic set/clear operations18 19- No polarity/level/edge settings20 21- No FIFO or priority encoder logic; software is expected to read all22 2-4 status words to determine which IRQs are pending23 24Required properties:25 26- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"27- reg: specifies the base physical address and size of the registers;28 the number of supported IRQs is inferred from the size argument29- interrupt-controller: identifies the node as an interrupt controller30- #interrupt-cells: specifies the number of cells needed to encode an interrupt31 source, should be 1.32- interrupts: specifies the interrupt line(s) in the interrupt-parent controller33 node; valid values depend on the type of parent interrupt controller34 35If multiple reg ranges and interrupt-parent entries are present on an SMP36system, the driver will allow IRQ SMP affinity to be set up through the37/proc/irq/ interface. In the simplest possible configuration, only one38reg range and one interrupt-parent is needed.39 40The driver operates in native CPU endian by default, there is no support for41specifying an alternative endianness.42 43Example:44 45periph_intc: interrupt-controller@10000000 {46 compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";47 reg = <0x10000020 0x20>,48 <0x10000040 0x20>;49 50 interrupt-controller;51 #interrupt-cells = <1>;52 53 interrupt-parent = <&cpu_intc>;54 interrupts = <2>, <3>;55};56