114 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale IRQSTEER Interrupt Multiplexer8 9maintainers:10 - Lucas Stach <l.stach@pengutronix.de>11 12properties:13 compatible:14 oneOf:15 - const: fsl,imx-irqsteer16 - items:17 - enum:18 - fsl,imx8m-irqsteer19 - fsl,imx8mp-irqsteer20 - fsl,imx8qm-irqsteer21 - fsl,imx8qxp-irqsteer22 - const: fsl,imx-irqsteer23 24 reg:25 maxItems: 126 27 interrupts:28 description: |29 should contain the up to 8 parent interrupt lines used to multiplex30 the input interrupts. They should be specified sequentially from31 output 0 to 7.32 items:33 - description: output interrupt 034 - description: output interrupt 135 - description: output interrupt 236 - description: output interrupt 337 - description: output interrupt 438 - description: output interrupt 539 - description: output interrupt 640 - description: output interrupt 741 minItems: 142 43 clocks:44 maxItems: 145 46 clock-names:47 const: ipg48 49 power-domains:50 maxItems: 151 52 interrupt-controller: true53 54 "#interrupt-cells":55 const: 156 57 fsl,channel:58 $ref: /schemas/types.yaml#/definitions/uint3259 description: |60 u32 value representing the output channel that all input IRQs should be61 steered into.62 63 fsl,num-irqs:64 $ref: /schemas/types.yaml#/definitions/uint3265 description: |66 u32 value representing the number of input interrupts of this channel,67 should be multiple of 32 input interrupts and up to 512 interrupts.68 69required:70 - compatible71 - reg72 - interrupts73 - clocks74 - clock-names75 - interrupt-controller76 - "#interrupt-cells"77 - fsl,channel78 - fsl,num-irqs79 80allOf:81 - if:82 properties:83 compatible:84 contains:85 enum:86 - fsl,imx8mp-irqsteer87 - fsl,imx8qm-irqsteer88 - fsl,imx8qxp-irqsteer89 then:90 required:91 - power-domains92 else:93 properties:94 power-domains: false95 96additionalProperties: false97 98examples:99 - |100 #include <dt-bindings/clock/imx8mq-clock.h>101 #include <dt-bindings/interrupt-controller/arm-gic.h>102 103 interrupt-controller@32e2d000 {104 compatible = "fsl,imx-irqsteer";105 reg = <0x32e2d000 0x1000>;106 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;107 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;108 clock-names = "ipg";109 fsl,channel = <0>;110 fsl,num-irqs = <64>;111 interrupt-controller;112 #interrupt-cells = <1>;113 };114