100 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller8 9maintainers:10 - Frank Li <Frank.Li@nxp.com>11 12description: |13 The Messaging Unit module enables two processors within the SoC to14 communicate and coordinate by passing messages (e.g. data, status15 and control) through the MU interface. The MU also provides the ability16 for one processor (A side) to signal the other processor (B side) using17 interrupts.18 19 Because the MU manages the messaging between processors, the MU uses20 different clocks (from each side of the different peripheral buses).21 Therefore, the MU must synchronize the accesses from one side to the22 other. The MU accomplishes synchronization using two sets of matching23 registers (Processor A-side, Processor B-side).24 25 MU can work as msi interrupt controller to do doorbell26 27allOf:28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#29 30properties:31 compatible:32 enum:33 - fsl,imx6sx-mu-msi34 - fsl,imx7ulp-mu-msi35 - fsl,imx8ulp-mu-msi36 - fsl,imx8ulp-mu-msi-s437 38 reg:39 items:40 - description: a side register base address41 - description: b side register base address42 43 reg-names:44 items:45 - const: processor-a-side46 - const: processor-b-side47 48 interrupts:49 description: a side interrupt number.50 maxItems: 151 52 clocks:53 maxItems: 154 55 power-domains:56 items:57 - description: a side power domain58 - description: b side power domain59 60 power-domain-names:61 items:62 - const: processor-a-side63 - const: processor-b-side64 65 interrupt-controller: true66 67 msi-controller: true68 69 "#msi-cells":70 const: 071 72required:73 - compatible74 - reg75 - interrupts76 - interrupt-controller77 - msi-controller78 - "#msi-cells"79 80additionalProperties: false81 82examples:83 - |84 #include <dt-bindings/interrupt-controller/arm-gic.h>85 #include <dt-bindings/firmware/imx/rsrc.h>86 87 msi-controller@5d270000 {88 compatible = "fsl,imx6sx-mu-msi";89 msi-controller;90 #msi-cells = <0>;91 interrupt-controller;92 reg = <0x5d270000 0x10000>, /* A side */93 <0x5d300000 0x10000>; /* B side */94 reg-names = "processor-a-side", "processor-b-side";95 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;96 power-domains = <&pd IMX_SC_R_MU_12A>,97 <&pd IMX_SC_R_MU_12B>;98 power-domain-names = "processor-a-side", "processor-b-side";99 };100