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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MStar Interrupt Controller8 9maintainers:10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>11 12description: |+13 MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy14 interrupt controllers that routes interrupts to the GIC.15 16 The HW block exposes a number of interrupt controllers, each17 can support up to 64 interrupts.18 19properties:20 compatible:21 const: mstar,mst-intc22 23 interrupt-controller: true24 25 "#interrupt-cells":26 const: 327 description: |28 Use the same format as specified by GIC in arm,gic.yaml.29 30 reg:31 maxItems: 132 33 mstar,irqs-map-range:34 description: |35 The range <start, end> of parent interrupt controller's interrupt36 lines that are hardwired to mstar interrupt controller.37 $ref: /schemas/types.yaml#/definitions/uint32-matrix38 items:39 minItems: 240 maxItems: 241 42 mstar,intc-no-eoi:43 description:44 Mark this controller has no End Of Interrupt(EOI) implementation.45 type: boolean46 47required:48 - compatible49 - reg50 - mstar,irqs-map-range51 52additionalProperties: false53 54examples:55 - |56 mst_intc0: interrupt-controller@1f2032d0 {57 compatible = "mstar,mst-intc";58 interrupt-controller;59 #interrupt-cells = <3>;60 interrupt-parent = <&gic>;61 reg = <0x1f2032d0 0x30>;62 mstar,irqs-map-range = <0 63>;63 };64...65