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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: PDC interrupt controller8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 12description: |13 Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a14 Power Domain Controller (PDC) that is on always-on domain. In addition to15 providing power control for the power domains, the hardware also has an16 interrupt controller that can be used to help detect edge low interrupts as17 well detect interrupts when the GIC is non-operational.18 19 GIC is parent interrupt controller at the highest level. Platform interrupt20 controller PDC is next in hierarchy, followed by others. Drivers requiring21 wakeup capabilities of their device interrupts routed through the PDC, must22 specify PDC as their interrupt controller and request the PDC port associated23 with the GIC interrupt. See example below.24 25properties:26 compatible:27 items:28 - enum:29 - qcom,qdu1000-pdc30 - qcom,sa8255p-pdc31 - qcom,sa8775p-pdc32 - qcom,sc7180-pdc33 - qcom,sc7280-pdc34 - qcom,sc8180x-pdc35 - qcom,sc8280xp-pdc36 - qcom,sdm670-pdc37 - qcom,sdm845-pdc38 - qcom,sdx55-pdc39 - qcom,sdx65-pdc40 - qcom,sdx75-pdc41 - qcom,sm4450-pdc42 - qcom,sm6350-pdc43 - qcom,sm8150-pdc44 - qcom,sm8250-pdc45 - qcom,sm8350-pdc46 - qcom,sm8450-pdc47 - qcom,sm8550-pdc48 - qcom,sm8650-pdc49 - qcom,x1e80100-pdc50 - const: qcom,pdc51 52 reg:53 minItems: 154 items:55 - description: PDC base register region56 - description: Edge or Level config register for SPI interrupts57 58 '#interrupt-cells':59 const: 260 61 interrupt-controller: true62 63 qcom,pdc-ranges:64 $ref: /schemas/types.yaml#/definitions/uint32-matrix65 minItems: 166 maxItems: 128 # no hard limit67 items:68 items:69 - description: starting PDC port70 - description: GIC hwirq number for the PDC port71 - description: number of interrupts in sequence72 description: |73 Specifies the PDC pin offset and the number of PDC ports.74 The tuples indicates the valid mapping of valid PDC ports75 and their hwirq mapping.76 77required:78 - compatible79 - reg80 - '#interrupt-cells'81 - interrupt-controller82 - qcom,pdc-ranges83 84additionalProperties: false85 86examples:87 - |88 #include <dt-bindings/interrupt-controller/irq.h>89 90 pdc: interrupt-controller@b220000 {91 compatible = "qcom,sdm845-pdc", "qcom,pdc";92 reg = <0xb220000 0x30000>;93 qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;94 #interrupt-cells = <2>;95 interrupt-parent = <&intc>;96 interrupt-controller;97 };98 99 wake-device {100 interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;101 };102