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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Realtek RTL SoC interrupt controller8 9description:10 Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC11 interrupt to be routed to one parent CPU (hardware) interrupt, or left12 disconnected.13 All connected input lines from SoC peripherals can be masked individually,14 and an interrupt status register is present to indicate which interrupts are15 pending.16 17maintainers:18 - Birger Koblitz <mail@birger-koblitz.de>19 - Bert Vermeulen <bert@biot.com>20 - John Crispin <john@phrozen.org>21 22properties:23 compatible:24 oneOf:25 - items:26 - enum:27 - realtek,rtl8380-intc28 - realtek,rtl9300-intc29 - const: realtek,rtl-intc30 - const: realtek,rtl-intc31 deprecated: true32 33 "#interrupt-cells":34 description:35 SoC interrupt line index.36 const: 137 38 reg:39 minItems: 140 items:41 - description: vpe0 registers42 - description: vpe1 registers43 44 interrupts:45 minItems: 146 maxItems: 1547 description:48 List of parent interrupts, in the order that they are connected to this49 interrupt router's outputs, starting at the first output.50 51 interrupt-controller: true52 53 interrupt-map:54 deprecated: true55 description: Describes mapping from SoC interrupts to CPU interrupts56 57required:58 - compatible59 - reg60 - "#interrupt-cells"61 - interrupt-controller62 63allOf:64 - if:65 properties:66 compatible:67 const: realtek,rtl-intc68 then:69 properties:70 "#address-cells":71 const: 072 required:73 - "#address-cells"74 - interrupt-map75 else:76 required:77 - interrupts78 - if:79 properties:80 compatible:81 contains:82 const: realtek,rtl9300-intc83 then:84 properties:85 reg:86 minItems: 287 maxItems: 288 else:89 properties:90 reg:91 maxItems: 192 93additionalProperties: false94 95examples:96 - |97 interrupt-controller@3000 {98 compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";99 #interrupt-cells = <1>;100 interrupt-controller;101 reg = <0x3000 0x18>;102 103 interrupt-parent = <&cpuintc>;104 interrupts = <2>, <3>, <4>, <5>, <6>;105 };106