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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)8 9maintainers:10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>11 - Geert Uytterhoeven <geert+renesas@glider.be>12 13description: |14 IA55 performs various interrupt controls including synchronization for the external15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral16 interrupts output by each IP. And it notifies the interrupt to the GIC17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and20 stand-up edge detection interrupts)21 22properties:23 compatible:24 oneOf:25 - items:26 - enum:27 - renesas,r9a07g043u-irqc # RZ/G2UL28 - renesas,r9a07g044-irqc # RZ/G2{L,LC}29 - renesas,r9a07g054-irqc # RZ/V2L30 - renesas,r9a08g045-irqc # RZ/G3S31 - const: renesas,rzg2l-irqc32 33 - const: renesas,r9a07g043f-irqc # RZ/Five34 35 '#interrupt-cells':36 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second38 cell is used to specify the flag.39 const: 240 41 '#address-cells':42 const: 043 44 interrupt-controller: true45 46 reg:47 maxItems: 148 49 interrupts:50 minItems: 4551 items:52 - description: NMI interrupt53 - description: IRQ0 interrupt54 - description: IRQ1 interrupt55 - description: IRQ2 interrupt56 - description: IRQ3 interrupt57 - description: IRQ4 interrupt58 - description: IRQ5 interrupt59 - description: IRQ6 interrupt60 - description: IRQ7 interrupt61 - description: GPIO interrupt, TINT062 - description: GPIO interrupt, TINT163 - description: GPIO interrupt, TINT264 - description: GPIO interrupt, TINT365 - description: GPIO interrupt, TINT466 - description: GPIO interrupt, TINT567 - description: GPIO interrupt, TINT668 - description: GPIO interrupt, TINT769 - description: GPIO interrupt, TINT870 - description: GPIO interrupt, TINT971 - description: GPIO interrupt, TINT1072 - description: GPIO interrupt, TINT1173 - description: GPIO interrupt, TINT1274 - description: GPIO interrupt, TINT1375 - description: GPIO interrupt, TINT1476 - description: GPIO interrupt, TINT1577 - description: GPIO interrupt, TINT1678 - description: GPIO interrupt, TINT1779 - description: GPIO interrupt, TINT1880 - description: GPIO interrupt, TINT1981 - description: GPIO interrupt, TINT2082 - description: GPIO interrupt, TINT2183 - description: GPIO interrupt, TINT2284 - description: GPIO interrupt, TINT2385 - description: GPIO interrupt, TINT2486 - description: GPIO interrupt, TINT2587 - description: GPIO interrupt, TINT2688 - description: GPIO interrupt, TINT2789 - description: GPIO interrupt, TINT2890 - description: GPIO interrupt, TINT2991 - description: GPIO interrupt, TINT3092 - description: GPIO interrupt, TINT3193 - description: Bus error interrupt94 - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt95 - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt96 - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt97 - description: ECCRAM1 1bit error interrupt98 - description: ECCRAM1 2bit error interrupt99 - description: ECCRAM1 error overflow interrupt100 101 interrupt-names:102 minItems: 45103 items:104 - const: nmi105 - const: irq0106 - const: irq1107 - const: irq2108 - const: irq3109 - const: irq4110 - const: irq5111 - const: irq6112 - const: irq7113 - const: tint0114 - const: tint1115 - const: tint2116 - const: tint3117 - const: tint4118 - const: tint5119 - const: tint6120 - const: tint7121 - const: tint8122 - const: tint9123 - const: tint10124 - const: tint11125 - const: tint12126 - const: tint13127 - const: tint14128 - const: tint15129 - const: tint16130 - const: tint17131 - const: tint18132 - const: tint19133 - const: tint20134 - const: tint21135 - const: tint22136 - const: tint23137 - const: tint24138 - const: tint25139 - const: tint26140 - const: tint27141 - const: tint28142 - const: tint29143 - const: tint30144 - const: tint31145 - const: bus-err146 - const: ec7tie1-0147 - const: ec7tie2-0148 - const: ec7tiovf-0149 - const: ec7tie1-1150 - const: ec7tie2-1151 - const: ec7tiovf-1152 153 clocks:154 maxItems: 2155 156 clock-names:157 items:158 - const: clk159 - const: pclk160 161 power-domains:162 maxItems: 1163 164 resets:165 maxItems: 1166 167required:168 - compatible169 - '#interrupt-cells'170 - '#address-cells'171 - interrupt-controller172 - reg173 - interrupts174 - interrupt-names175 - clocks176 - clock-names177 - power-domains178 - resets179 180allOf:181 - $ref: /schemas/interrupt-controller.yaml#182 183 - if:184 properties:185 compatible:186 contains:187 enum:188 - renesas,r9a08g045-irqc189 then:190 properties:191 interrupts:192 maxItems: 45193 interrupt-names:194 maxItems: 45195 else:196 properties:197 interrupts:198 minItems: 48199 interrupt-names:200 minItems: 48201 202unevaluatedProperties: false203 204examples:205 - |206 #include <dt-bindings/interrupt-controller/arm-gic.h>207 #include <dt-bindings/clock/r9a07g044-cpg.h>208 209 irqc: interrupt-controller@110a0000 {210 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";211 reg = <0x110a0000 0x10000>;212 #interrupt-cells = <2>;213 #address-cells = <0>;214 interrupt-controller;215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,216 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,217 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,218 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,219 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,220 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,221 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,222 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,223 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,224 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,225 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,226 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,227 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,228 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,229 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,230 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,231 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,232 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,233 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,234 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,235 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,236 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,237 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,238 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,239 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,240 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,241 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,242 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,243 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,244 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,245 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,246 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,247 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,248 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,249 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,250 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,251 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,252 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,253 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,254 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,255 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,256 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,257 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,258 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,259 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,260 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,261 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,262 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;263 interrupt-names = "nmi",264 "irq0", "irq1", "irq2", "irq3",265 "irq4", "irq5", "irq6", "irq7",266 "tint0", "tint1", "tint2", "tint3",267 "tint4", "tint5", "tint6", "tint7",268 "tint8", "tint9", "tint10", "tint11",269 "tint12", "tint13", "tint14", "tint15",270 "tint16", "tint17", "tint18", "tint19",271 "tint20", "tint21", "tint22", "tint23",272 "tint24", "tint25", "tint26", "tint27",273 "tint28", "tint29", "tint30", "tint31",274 "bus-err", "ec7tie1-0", "ec7tie2-0",275 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",276 "ec7tiovf-1";277 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,278 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;279 clock-names = "clk", "pclk";280 power-domains = <&cpg>;281 resets = <&cpg R9A07G044_IA55_RESETN>;282 };283