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1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: RISC-V Hart-Level Interrupt Controller (HLIC)8 9description:10 RISC-V cores include Control Status Registers (CSRs) which are local to11 each CPU core (HART in RISC-V terminology) and can be read or written by12 software. Some of these CSRs are used to control local interrupts connected13 to the core. Every interrupt is ultimately routed through a hart's HLIC14 before it interrupts that hart.15 16 The RISC-V supervisor ISA manual specifies three interrupt sources that are17 attached to every HLIC namely software interrupts, the timer interrupt, and18 external interrupts. Software interrupts are used to send IPIs between19 cores. The timer interrupt comes from an architecturally mandated real-20 time timer that is controlled via Supervisor Binary Interface (SBI) calls21 and CSR reads. External interrupts connect all other device interrupts to22 the HLIC, which are routed via the platform-level interrupt controller23 (PLIC).24 25 All RISC-V systems that conform to the supervisor ISA specification are26 required to have a HLIC with these three interrupt sources present. Since27 the interrupt map is defined by the ISA it's not listed in the HLIC's device28 tree entry, though external interrupt controllers (like the PLIC, for29 example) will need to define how their interrupts map to the relevant HLICs.30 This means a PLIC interrupt property will typically list the HLICs for all31 present HARTs in the system.32 33maintainers:34 - Palmer Dabbelt <palmer@dabbelt.com>35 - Paul Walmsley <paul.walmsley@sifive.com>36 37properties:38 compatible:39 oneOf:40 - items:41 - const: andestech,cpu-intc42 - const: riscv,cpu-intc43 - const: riscv,cpu-intc44 45 interrupt-controller: true46 47 '#interrupt-cells':48 const: 149 description: |50 The interrupt sources are defined by the RISC-V supervisor ISA manual,51 with only the following three interrupts being defined for52 supervisor mode:53 - Source 1 is the supervisor software interrupt, which can be sent by54 an SBI call and is reserved for use by software.55 - Source 5 is the supervisor timer interrupt, which can be configured56 by SBI calls and implements a one-shot timer.57 - Source 9 is the supervisor external interrupt, which chains to all58 other device interrupts.59 60required:61 - compatible62 - '#interrupt-cells'63 - interrupt-controller64 65additionalProperties: false66 67examples:68 - |69 interrupt-controller {70 #interrupt-cells = <1>;71 compatible = "riscv,cpu-intc";72 interrupt-controller;73 };74