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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2# Copyright (C) 2020 SiFive, Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: SiFive Platform-Level Interrupt Controller (PLIC)9 10description:11 SiFive SoCs and other RISC-V SoCs include an implementation of the12 Platform-Level Interrupt Controller (PLIC) high-level specification in13 the RISC-V Privileged Architecture specification. The PLIC connects all14 external interrupts in the system to all hart contexts in the system, via15 the external interrupt source in each hart.16 17 A hart context is a privilege mode in a hardware execution thread. For example,18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two19 privilege modes per hart; machine mode and supervisor mode.20 21 Each interrupt can be enabled on per-context basis. Any context can claim22 a pending enabled interrupt and then release it once it has been handled.23 24 Each interrupt has a configurable priority. Higher priority interrupts are25 serviced first. Each context can specify a priority threshold. Interrupts26 with priority below this threshold will not cause the PLIC to raise its27 interrupt line leading to the context.28 29 The PLIC supports both edge-triggered and level-triggered interrupts. For30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges31 seen while an interrupt handler is active; the PLIC may either queue them or32 ignore them. In the first case, handlers are oblivious to the trigger type, so33 it is not included in the interrupt specifier. In the second case, software34 needs to know the trigger type, so it can reorder the interrupt flow to avoid35 missing interrupts. This special handling is needed by at least the Renesas36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.37 38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that40 contains a specific memory layout, which is documented in chapter 8 of the41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.42 43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the44 T-HEAD PLIC implementation requires setting a delegation bit to allow access45 from S-mode. So add thead,c900-plic to distinguish them.46 47maintainers:48 - Paul Walmsley <paul.walmsley@sifive.com>49 - Palmer Dabbelt <palmer@dabbelt.com>50 51properties:52 compatible:53 oneOf:54 - items:55 - enum:56 - renesas,r9a07g043-plic57 - const: andestech,nceplic10058 - items:59 - enum:60 - canaan,k210-plic61 - sifive,fu540-c000-plic62 - starfive,jh7100-plic63 - starfive,jh7110-plic64 - const: sifive,plic-1.0.065 - items:66 - enum:67 - allwinner,sun20i-d1-plic68 - sophgo,cv1800b-plic69 - sophgo,cv1812h-plic70 - sophgo,sg2002-plic71 - sophgo,sg2042-plic72 - thead,th1520-plic73 - const: thead,c900-plic74 - items:75 - const: sifive,plic-1.0.076 - const: riscv,plic077 deprecated: true78 description: For the QEMU virt machine only79 80 reg:81 maxItems: 182 83 '#address-cells':84 const: 085 86 '#interrupt-cells': true87 88 interrupt-controller: true89 90 interrupts-extended:91 minItems: 192 maxItems: 1587293 description:94 Specifies which contexts are connected to the PLIC, with "-1" specifying95 that a context is not present. Each node pointed to should be a96 riscv,cpu-intc node, which has a riscv node as parent.97 98 riscv,ndev:99 $ref: /schemas/types.yaml#/definitions/uint32100 description:101 Specifies how many external interrupts are supported by this controller.102 103 clocks: true104 105 power-domains: true106 107 resets: true108 109required:110 - compatible111 - '#address-cells'112 - '#interrupt-cells'113 - interrupt-controller114 - reg115 - interrupts-extended116 - riscv,ndev117 118allOf:119 - if:120 properties:121 compatible:122 contains:123 enum:124 - andestech,nceplic100125 - thead,c900-plic126 127 then:128 properties:129 '#interrupt-cells':130 const: 2131 132 else:133 properties:134 '#interrupt-cells':135 const: 1136 137 - if:138 properties:139 compatible:140 contains:141 const: renesas,r9a07g043-plic142 143 then:144 properties:145 clocks:146 maxItems: 1147 148 power-domains:149 maxItems: 1150 151 resets:152 maxItems: 1153 154 required:155 - clocks156 - power-domains157 - resets158 159additionalProperties: false160 161examples:162 - |163 plic: interrupt-controller@c000000 {164 #address-cells = <0>;165 #interrupt-cells = <1>;166 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";167 interrupt-controller;168 interrupts-extended = <&cpu0_intc 11>,169 <&cpu1_intc 11>, <&cpu1_intc 9>,170 <&cpu2_intc 11>, <&cpu2_intc 9>,171 <&cpu3_intc 11>, <&cpu3_intc 9>,172 <&cpu4_intc 11>, <&cpu4_intc 9>;173 reg = <0xc000000 0x4000000>;174 riscv,ndev = <10>;175 };176