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1* ARC-HS Interrupt Distribution Unit2 3 This optional 2nd level interrupt controller can be used in SMP configurations4 for dynamic IRQ routing, load balancing of common/external IRQs towards core5 intc.6 7Properties:8 9- compatible: "snps,archs-idu-intc"10- interrupt-controller: This is an interrupt controller.11- #interrupt-cells: Must be <1> or <2>.12 13 Value of the first cell specifies the "common" IRQ from peripheral to IDU.14 Number N of the particular interrupt line of IDU corresponds to the line N+2415 of the core interrupt controller.16 17 The (optional) second cell specifies any of the following flags:18 - bits[3:0] trigger type and level flags19 1 = low-to-high edge triggered20 2 = NOT SUPPORTED (high-to-low edge triggered)21 4 = active high level-sensitive <<< DEFAULT22 8 = NOT SUPPORTED (active low level-sensitive)23 When no second cell is specified, the interrupt is assumed to be level24 sensitive.25 26 The interrupt controller is accessed via the special ARC AUX register27 interface, hence "reg" property is not specified.28 29Example:30 core_intc: core-interrupt-controller {31 compatible = "snps,archs-intc";32 interrupt-controller;33 #interrupt-cells = <1>;34 };35 36 idu_intc: idu-interrupt-controller {37 compatible = "snps,archs-idu-intc";38 interrupt-controller;39 interrupt-parent = <&core_intc>;40 #interrupt-cells = <1>;41 };42 43 some_device: serial@c0fc1000 {44 interrupt-parent = <&idu_intc>;45 interrupts = <0>; /* upstream idu IRQ #24 */46 };47