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1* SPEAr Shared IRQ layer (shirq)2 3SPEAr3xx architecture includes shared/multiplexed irqs for certain set4of devices. The multiplexor provides a single interrupt to parent5interrupt controller (VIC) on behalf of a group of devices.6 7There can be multiple groups available on SPEAr3xx variants but not8exceeding 4. The number of devices in a group can differ, further they9may share same set of status/mask registers spanning across different10bit masks. Also in some cases the group may not have enable or other11registers. This makes software little complex.12 13A single node in the device tree is used to describe the shared14interrupt multiplexor (one node for all groups). A group in the15interrupt controller shares config/control registers with other groups.16For example, a 32-bit interrupt enable/disable config register can17accommodate up to 4 interrupt groups.18 19Required properties:20 - compatible: should be, either of21 - "st,spear300-shirq"22 - "st,spear310-shirq"23 - "st,spear320-shirq"24 - interrupt-controller: Identifies the node as an interrupt controller.25 - #interrupt-cells: should be <1> which basically contains the offset26 (starting from 0) of interrupts for all the groups.27 - reg: Base address and size of shirq registers.28 - interrupts: The list of interrupts generated by the groups which are29 then connected to a parent interrupt controller. Each group is30 associated with one of the interrupts, hence number of interrupts (to31 parent) is equal to number of groups. The format of the interrupt32 specifier depends in the interrupt parent controller.33 34Example:35 36The following is an example from the SPEAr320 SoC dtsi file.37 38shirq: interrupt-controller@b3000000 {39 compatible = "st,spear320-shirq";40 reg = <0xb3000000 0x1000>;41 interrupts = <28 29 30 1>;42 #interrupt-cells = <1>;43 interrupt-controller;44};45