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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STi System Configuration Controlled IRQs8 9maintainers:10 - Patrice Chotard <patrice.chotard@foss.st.com>11 12description:13 On STi based systems; External, CTI (Core Sight), PMU (Performance14 Management), and PL310 L2 Cache IRQs are controlled using System15 Configuration registers. This device is used to unmask them prior to use.16 17properties:18 compatible:19 const: st,stih407-irq-syscfg20 21 st,syscfg:22 description: Phandle to Cortex-A9 IRQ system config registers23 $ref: /schemas/types.yaml#/definitions/phandle24 25 st,irq-device:26 description: Array of IRQs to enable.27 $ref: /schemas/types.yaml#/definitions/uint32-array28 items:29 - description: Enable the IRQ of the channel one.30 - description: Enable the IRQ of the channel two.31 32 st,fiq-device:33 description: Array of FIQs to enable.34 $ref: /schemas/types.yaml#/definitions/uint32-array35 items:36 - description: Enable the IRQ of the channel one.37 - description: Enable the IRQ of the channel two.38 39 st,invert-ext:40 description: External IRQs can be inverted at will. This property inverts41 these three IRQs using bitwise logic, each one being encoded respectively42 on the first, second and fourth bit.43 $ref: /schemas/types.yaml#/definitions/uint3244 enum: [ 1, 2, 3, 4, 5, 6 ]45 46required:47 - compatible48 - st,syscfg49 - st,irq-device50 - st,fiq-device51 52additionalProperties: false53 54examples:55 - |56 #include <dt-bindings/interrupt-controller/irq-st.h>57 irq-syscfg {58 compatible = "st,stih407-irq-syscfg";59 st,syscfg = <&syscfg_cpu>;60 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,61 <ST_IRQ_SYSCFG_PMU_1>;62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,63 <ST_IRQ_SYSCFG_DISABLED>;64 };65...66