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1Keystone 2 IRQ controller IP2 3On Keystone SOCs, DSP cores can send interrupts to ARM4host using the IRQ controller IP. It provides 28 IRQ signals to ARM.5The IRQ handler running on HOST OS can identify DSP signal source by6analyzing SRCCx bits in IPCARx registers. This is one of the component7used by the IPC mechanism used on Keystone SOCs.8 9Required Properties:10- compatible: should be "ti,keystone-irq"11- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to12 access device control registers and the offset inside13 device control registers range.14- interrupt-controller : Identifies the node as an interrupt controller15- #interrupt-cells : Specifies the number of cells needed to encode interrupt16 source should be 1.17- interrupts: interrupt reference to primary interrupt controller18 19Please refer to interrupts.txt in this directory for details of the common20Interrupt Controllers bindings used by client devices.21 22Example:23 kirq0: keystone_irq0@26202a0 {24 compatible = "ti,keystone-irq";25 ti,syscon-dev = <&devctrl 0x2a0>;26 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;27 interrupt-controller;28 #interrupt-cells = <1>;29 };30 31 dsp0: dsp0 {32 compatible = "linux,rproc-user";33 ...34 interrupt-parent = <&kirq0>;35 interrupts = <10 2>;36 };37