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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Texas Instruments K3 Interrupt Aggregator8 9maintainers:10 - Lokesh Vutla <lokeshvutla@ti.com>11 12allOf:13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#14 15description: |16 The Interrupt Aggregator (INTA) provides a centralized machine17 which handles the termination of system events to that they can18 be coherently processed by the host(s) in the system. A maximum19 of 64 events can be mapped to a single interrupt.20 21 Interrupt Aggregator22 +-----------------------------------------+23 | Intmap VINT |24 | +--------------+ +------------+ |25 m ------>| | vint | bit | | 0 |.....|63| vint0 |26 . | +--------------+ +------------+ | +------+27 . | . . | | HOST |28 Globalevents ------>| . . |----->| IRQ |29 . | . . | | CTRL |30 . | . . | +------+31 n ------>| +--------------+ +------------+ |32 | | vint | bit | | 0 |.....|63| vintx |33 | +--------------+ +------------+ |34 | |35 | Unmap |36 | +--------------+ |37 Unmapped events ---->| | umapidx |-------------------------> Globalevents38 | +--------------+ |39 | |40 +-----------------------------------------+41 42 Configuration of these Intmap registers that maps global events to vint is43 done by a system controller (like the Device Memory and Security Controller44 on AM654 SoC). Driver should request the system controller to get the range45 of global events and vints assigned to the requesting host. Management46 of these requested resources should be handled by driver and requests47 system controller to map specific global event to vint, bit pair.48 49 Communication between the host processor running an OS and the system50 controller happens through a protocol called TI System Control Interface51 (TISCI protocol).52 53properties:54 compatible:55 const: ti,sci-inta56 57 reg:58 maxItems: 159 60 interrupt-controller: true61 62 '#interrupt-cells':63 const: 064 65 msi-controller: true66 67 ti,interrupt-ranges:68 $ref: /schemas/types.yaml#/definitions/uint32-matrix69 description: |70 Interrupt ranges that converts the INTA output hw irq numbers71 to parents's input interrupt numbers.72 items:73 items:74 - description: |75 "output_irq" specifies the base for inta output irq76 - description: |77 "parent's input irq" specifies the base for parent irq78 - description: |79 "limit" specifies the limit for translation80 81 ti,unmapped-event-sources:82 $ref: /schemas/types.yaml#/definitions/phandle-array83 items:84 maxItems: 185 description:86 Array of phandles to DMA controllers where the unmapped events originate.87 88 power-domains:89 maxItems: 190 91required:92 - compatible93 - reg94 - interrupt-controller95 - msi-controller96 - ti,sci97 - ti,sci-dev-id98 - ti,interrupt-ranges99 100unevaluatedProperties: false101 102examples:103 - |104 bus {105 #address-cells = <2>;106 #size-cells = <2>;107 108 main_udmass_inta: msi-controller@33d00000 {109 compatible = "ti,sci-inta";110 reg = <0x0 0x33d00000 0x0 0x100000>;111 interrupt-controller;112 msi-controller;113 interrupt-parent = <&main_navss_intr>;114 ti,sci = <&dmsc>;115 ti,sci-dev-id = <179>;116 ti,interrupt-ranges = <0 0 256>;117 };118 };119