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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Texas Instruments K3 Interrupt Router8 9maintainers:10 - Lokesh Vutla <lokeshvutla@ti.com>11 12allOf:13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#14 15description: |16 The Interrupt Router (INTR) module provides a mechanism to mux M17 interrupt inputs to N interrupt outputs, where all M inputs are selectable18 to be driven per N output. An Interrupt Router can either handle edge19 triggered or level triggered interrupts and that is fixed in hardware.20 21 Interrupt Router22 +----------------------+23 | Inputs Outputs |24 +-------+ | +------+ +-----+ |25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ26 +-------+ | +------+ +-----+ | controller27 | . . | +-------+28 +-------+ | . . |----->| IRQ |29 | INTA |----------->| . . | +-------+30 +-------+ | . +-----+ |31 | +------+ | N | |32 | | irqM | +-----+ |33 | +------+ |34 | |35 +----------------------+36 37 There is one register per output (MUXCNTL_N) that controls the selection.38 Configuration of these MUXCNTL_N registers is done by a system controller39 (like the Device Memory and Security Controller on K3 AM654 SoC). System40 controller will keep track of the used and unused registers within the Router.41 Driver should request the system controller to get the range of GIC IRQs42 assigned to the requesting hosts. It is the drivers responsibility to keep43 track of Host IRQs.44 45 Communication between the host processor running an OS and the system46 controller happens through a protocol called TI System Control Interface47 (TISCI protocol).48 49properties:50 compatible:51 const: ti,sci-intr52 53 ti,intr-trigger-type:54 $ref: /schemas/types.yaml#/definitions/uint3255 enum: [1, 4]56 description: |57 Should be one of the following.58 1 = If intr supports edge triggered interrupts.59 4 = If intr supports level triggered interrupts.60 61 reg:62 maxItems: 163 64 interrupt-controller: true65 66 '#interrupt-cells':67 const: 168 description: |69 The 1st cell should contain interrupt router input hw number.70 71 ti,interrupt-ranges:72 $ref: /schemas/types.yaml#/definitions/uint32-matrix73 description: |74 Interrupt ranges that converts the INTR output hw irq numbers75 to parents's input interrupt numbers.76 items:77 items:78 - description: |79 "output_irq" specifies the base for intr output irq80 - description: |81 "parent's input irq" specifies the base for parent irq82 - description: |83 "limit" specifies the limit for translation84 85required:86 - compatible87 - ti,intr-trigger-type88 - interrupt-controller89 - '#interrupt-cells'90 - ti,sci91 - ti,sci-dev-id92 - ti,interrupt-ranges93 94unevaluatedProperties: false95 96examples:97 - |98 main_gpio_intr: interrupt-controller0 {99 compatible = "ti,sci-intr";100 ti,intr-trigger-type = <1>;101 interrupt-controller;102 interrupt-parent = <&gic500>;103 #interrupt-cells = <1>;104 ti,sci = <&dmsc>;105 ti,sci-dev-id = <131>;106 ti,interrupt-ranges = <0 360 32>;107 };108