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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM System MMU Architecture Implementation8 9maintainers:10 - Will Deacon <will@kernel.org>11 - Robin Murphy <Robin.Murphy@arm.com>12 13description: |+14 ARM SoCs may contain an implementation of the ARM System Memory15 Management Unit Architecture, which can be used to provide 1 or 2 stages16 of address translation to bus masters external to the CPU.17 18 The SMMU may also raise interrupts in response to various fault19 conditions.20 21properties:22 $nodename:23 pattern: "^iommu@[0-9a-f]*"24 compatible:25 oneOf:26 - description: Qcom SoCs implementing "arm,smmu-v2"27 items:28 - enum:29 - qcom,msm8996-smmu-v230 - qcom,msm8998-smmu-v231 - qcom,sdm630-smmu-v232 - qcom,sm6375-smmu-v233 - const: qcom,smmu-v234 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"36 items:37 - enum:38 - qcom,qcm2290-smmu-50039 - qcom,qcs8300-smmu-50040 - qcom,qdu1000-smmu-50041 - qcom,sa8255p-smmu-50042 - qcom,sa8775p-smmu-50043 - qcom,sc7180-smmu-50044 - qcom,sc7280-smmu-50045 - qcom,sc8180x-smmu-50046 - qcom,sc8280xp-smmu-50047 - qcom,sdm670-smmu-50048 - qcom,sdm845-smmu-50049 - qcom,sdx55-smmu-50050 - qcom,sdx65-smmu-50051 - qcom,sdx75-smmu-50052 - qcom,sm6115-smmu-50053 - qcom,sm6125-smmu-50054 - qcom,sm6350-smmu-50055 - qcom,sm6375-smmu-50056 - qcom,sm8150-smmu-50057 - qcom,sm8250-smmu-50058 - qcom,sm8350-smmu-50059 - qcom,sm8450-smmu-50060 - qcom,sm8550-smmu-50061 - qcom,sm8650-smmu-50062 - qcom,x1e80100-smmu-50063 - const: qcom,smmu-50064 - const: arm,mmu-50065 66 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)67 deprecated: true68 items:69 # Do not add additional SoC to this list. Instead use two previous lists.70 - enum:71 - qcom,qcm2290-smmu-50072 - qcom,sc7180-smmu-50073 - qcom,sc7280-smmu-50074 - qcom,sc8180x-smmu-50075 - qcom,sc8280xp-smmu-50076 - qcom,sdm845-smmu-50077 - qcom,sm6115-smmu-50078 - qcom,sm6350-smmu-50079 - qcom,sm6375-smmu-50080 - qcom,sm8150-smmu-50081 - qcom,sm8250-smmu-50082 - qcom,sm8350-smmu-50083 - qcom,sm8450-smmu-50084 - const: arm,mmu-50085 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"86 items:87 - enum:88 - qcom,qcm2290-smmu-50089 - qcom,sa8255p-smmu-50090 - qcom,sa8775p-smmu-50091 - qcom,sc7280-smmu-50092 - qcom,sc8180x-smmu-50093 - qcom,sc8280xp-smmu-50094 - qcom,sm6115-smmu-50095 - qcom,sm6125-smmu-50096 - qcom,sm8150-smmu-50097 - qcom,sm8250-smmu-50098 - qcom,sm8350-smmu-50099 - qcom,sm8450-smmu-500100 - qcom,sm8550-smmu-500101 - qcom,sm8650-smmu-500102 - qcom,x1e80100-smmu-500103 - const: qcom,adreno-smmu104 - const: qcom,smmu-500105 - const: arm,mmu-500106 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)107 deprecated: true108 items:109 # Do not add additional SoC to this list. Instead use previous list.110 - enum:111 - qcom,sc7280-smmu-500112 - qcom,sm8150-smmu-500113 - qcom,sm8250-smmu-500114 - const: qcom,adreno-smmu115 - const: arm,mmu-500116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"117 items:118 - enum:119 - qcom,msm8996-smmu-v2120 - qcom,sc7180-smmu-v2121 - qcom,sdm630-smmu-v2122 - qcom,sdm845-smmu-v2123 - qcom,sm6350-smmu-v2124 - qcom,sm7150-smmu-v2125 - const: qcom,adreno-smmu126 - const: qcom,smmu-v2127 - description: Qcom Adreno GPUs on Google Cheza platform128 items:129 - const: qcom,sdm845-smmu-v2130 - const: qcom,smmu-v2131 - description: Marvell SoCs implementing "arm,mmu-500"132 items:133 - const: marvell,ap806-smmu-500134 - const: arm,mmu-500135 - description: NVIDIA SoCs that require memory controller interaction136 and may program multiple ARM MMU-500s identically with the memory137 controller interleaving translations between multiple instances138 for improved performance.139 items:140 - enum:141 - nvidia,tegra186-smmu142 - nvidia,tegra194-smmu143 - nvidia,tegra234-smmu144 - const: nvidia,smmu-500145 - items:146 - const: arm,mmu-500147 - const: arm,smmu-v2148 - items:149 - enum:150 - arm,mmu-400151 - arm,mmu-401152 - const: arm,smmu-v1153 - enum:154 - arm,smmu-v1155 - arm,smmu-v2156 - arm,mmu-400157 - arm,mmu-401158 - arm,mmu-500159 - cavium,smmu-v2160 161 reg:162 minItems: 1163 maxItems: 2164 165 '#global-interrupts':166 description: The number of global interrupts exposed by the device.167 $ref: /schemas/types.yaml#/definitions/uint32168 minimum: 0169 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters170 171 '#iommu-cells':172 enum: [ 1, 2 ]173 description: |174 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a175 value of 1, each IOMMU specifier represents a distinct stream ID emitted176 by that device into the relevant SMMU.177 178 SMMUs with stream matching support and complex masters may use a value of179 2, where the second cell of the IOMMU specifier represents an SMR mask to180 combine with the ID in the first cell. Care must be taken to ensure the181 set of matched IDs does not result in conflicts.182 183 interrupts:184 minItems: 1185 maxItems: 388 # 260 plus 128 contexts186 description: |187 Interrupt list, with the first #global-interrupts entries corresponding to188 the global interrupts and any following entries corresponding to context189 interrupts, specified in order of their indexing by the SMMU.190 191 For SMMUv2 implementations, there must be exactly one interrupt per192 context bank. In the case of a single, combined interrupt, it must be193 listed multiple times.194 195 dma-coherent:196 description: |197 Present if page table walks made by the SMMU are cache coherent with the198 CPU.199 200 NOTE: this only applies to the SMMU itself, not masters connected201 upstream of the SMMU.202 203 calxeda,smmu-secure-config-access:204 type: boolean205 description:206 Enable proper handling of buggy implementations that always use secure207 access to SMMU configuration registers. In this case non-secure aliases of208 secure registers have to be used during SMMU configuration.209 210 stream-match-mask:211 $ref: /schemas/types.yaml#/definitions/uint32212 description: |213 For SMMUs supporting stream matching and using #iommu-cells = <1>,214 specifies a mask of bits to ignore when matching stream IDs (e.g. this may215 be programmed into the SMRn.MASK field of every stream match register216 used). For cases where it is desirable to ignore some portion of every217 Stream ID (e.g. for certain MMU-500 configurations given globally unique218 input IDs). This property is not valid for SMMUs using stream indexing, or219 using stream matching with #iommu-cells = <2>, and may be ignored if220 present in such cases.221 222 clock-names:223 minItems: 1224 maxItems: 7225 226 clocks:227 minItems: 1228 maxItems: 7229 230 power-domains:231 minItems: 1232 maxItems: 3233 234 nvidia,memory-controller:235 description: |236 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.237 The memory controller needs to be programmed with a mapping of memory238 client IDs to ARM SMMU stream IDs.239 240 If this property is absent, the mapping programmed by early firmware241 will be used and it is not guaranteed that IOMMU translations will be242 enabled for any given device.243 $ref: /schemas/types.yaml#/definitions/phandle244 245required:246 - compatible247 - reg248 - '#global-interrupts'249 - '#iommu-cells'250 - interrupts251 252additionalProperties: false253 254allOf:255 - if:256 properties:257 compatible:258 contains:259 enum:260 - nvidia,tegra186-smmu261 - nvidia,tegra194-smmu262 - nvidia,tegra234-smmu263 then:264 properties:265 reg:266 minItems: 1267 maxItems: 2268 269 # The reference to the memory controller is required to ensure that the270 # memory client to stream ID mapping can be done synchronously with the271 # IOMMU attachment.272 required:273 - nvidia,memory-controller274 else:275 properties:276 reg:277 maxItems: 1278 279 - if:280 properties:281 compatible:282 contains:283 enum:284 - qcom,msm8998-smmu-v2285 - qcom,sdm630-smmu-v2286 then:287 anyOf:288 - properties:289 clock-names:290 items:291 - const: bus292 clocks:293 items:294 - description: bus clock required for downstream bus access and for295 the smmu ptw296 - properties:297 clock-names:298 items:299 - const: iface300 - const: mem301 - const: mem_iface302 clocks:303 items:304 - description: interface clock required to access smmu's registers305 through the TCU's programming interface.306 - description: bus clock required for memory access307 - description: bus clock required for GPU memory access308 - properties:309 clock-names:310 items:311 - const: iface-mm312 - const: iface-smmu313 - const: bus-smmu314 clocks:315 items:316 - description: interface clock required to access mnoc's registers317 through the TCU's programming interface.318 - description: interface clock required to access smmu's registers319 through the TCU's programming interface.320 - description: bus clock required for the smmu ptw321 322 - if:323 properties:324 compatible:325 contains:326 enum:327 - qcom,sm6375-smmu-v2328 then:329 anyOf:330 - properties:331 clock-names:332 items:333 - const: bus334 clocks:335 items:336 - description: bus clock required for downstream bus access and for337 the smmu ptw338 - properties:339 clock-names:340 items:341 - const: iface342 - const: mem343 - const: mem_iface344 clocks:345 items:346 - description: interface clock required to access smmu's registers347 through the TCU's programming interface.348 - description: bus clock required for memory access349 - description: bus clock required for GPU memory access350 - properties:351 clock-names:352 items:353 - const: iface-mm354 - const: iface-smmu355 - const: bus-mm356 - const: bus-smmu357 clocks:358 items:359 - description: interface clock required to access mnoc's registers360 through the TCU's programming interface.361 - description: interface clock required to access smmu's registers362 through the TCU's programming interface.363 - description: bus clock required for downstream bus access364 - description: bus clock required for the smmu ptw365 366 - if:367 properties:368 compatible:369 contains:370 enum:371 - qcom,msm8996-smmu-v2372 - qcom,sc7180-smmu-v2373 - qcom,sdm845-smmu-v2374 then:375 properties:376 clock-names:377 items:378 - const: bus379 - const: iface380 381 clocks:382 items:383 - description: bus clock required for downstream bus access and for384 the smmu ptw385 - description: interface clock required to access smmu's registers386 through the TCU's programming interface.387 388 - if:389 properties:390 compatible:391 contains:392 enum:393 - qcom,sa8775p-smmu-500394 - qcom,sc7280-smmu-500395 - qcom,sc8280xp-smmu-500396 then:397 properties:398 clock-names:399 items:400 - const: gcc_gpu_memnoc_gfx_clk401 - const: gcc_gpu_snoc_dvm_gfx_clk402 - const: gpu_cc_ahb_clk403 - const: gpu_cc_hlos1_vote_gpu_smmu_clk404 - const: gpu_cc_cx_gmu_clk405 - const: gpu_cc_hub_cx_int_clk406 - const: gpu_cc_hub_aon_clk407 408 clocks:409 items:410 - description: GPU memnoc_gfx clock411 - description: GPU snoc_dvm_gfx clock412 - description: GPU ahb clock413 - description: GPU hlos1_vote_GPU smmu clock414 - description: GPU cx_gmu clock415 - description: GPU hub_cx_int clock416 - description: GPU hub_aon clock417 418 - if:419 properties:420 compatible:421 contains:422 enum:423 - qcom,sc8180x-smmu-500424 - qcom,sm6350-smmu-v2425 - qcom,sm7150-smmu-v2426 - qcom,sm8150-smmu-500427 - qcom,sm8250-smmu-500428 then:429 properties:430 clock-names:431 items:432 - const: ahb433 - const: bus434 - const: iface435 436 clocks:437 items:438 - description: bus clock required for AHB bus access439 - description: bus clock required for downstream bus access and for440 the smmu ptw441 - description: interface clock required to access smmu's registers442 through the TCU's programming interface.443 444 - if:445 properties:446 compatible:447 items:448 - enum:449 - qcom,sm8350-smmu-500450 - const: qcom,adreno-smmu451 - const: qcom,smmu-500452 - const: arm,mmu-500453 then:454 properties:455 clock-names:456 items:457 - const: bus458 - const: iface459 - const: ahb460 - const: hlos1_vote_gpu_smmu461 - const: cx_gmu462 - const: hub_cx_int463 - const: hub_aon464 clocks:465 minItems: 7466 maxItems: 7467 468 - if:469 properties:470 compatible:471 items:472 - enum:473 - qcom,qcm2290-smmu-500474 - qcom,sm6115-smmu-500475 - qcom,sm6125-smmu-500476 - const: qcom,adreno-smmu477 - const: qcom,smmu-500478 - const: arm,mmu-500479 then:480 properties:481 clock-names:482 items:483 - const: mem484 - const: hlos485 - const: iface486 487 clocks:488 items:489 - description: GPU memory bus clock490 - description: Voter clock required for HLOS SMMU access491 - description: Interface clock required for register access492 493 - if:494 properties:495 compatible:496 items:497 - const: qcom,sm8450-smmu-500498 - const: qcom,adreno-smmu499 - const: qcom,smmu-500500 - const: arm,mmu-500501 502 then:503 properties:504 clock-names:505 items:506 - const: gmu507 - const: hub508 - const: hlos509 - const: bus510 - const: iface511 - const: ahb512 513 clocks:514 items:515 - description: GMU clock516 - description: GPU HUB clock517 - description: HLOS vote clock518 - description: GPU memory bus clock519 - description: GPU SNoC bus clock520 - description: GPU AHB clock521 522 - if:523 properties:524 compatible:525 items:526 - enum:527 - qcom,sm8550-smmu-500528 - qcom,sm8650-smmu-500529 - qcom,x1e80100-smmu-500530 - const: qcom,adreno-smmu531 - const: qcom,smmu-500532 - const: arm,mmu-500533 then:534 properties:535 clock-names:536 items:537 - const: hlos538 - const: bus539 - const: iface540 - const: ahb541 542 clocks:543 items:544 - description: HLOS vote clock545 - description: GPU memory bus clock546 - description: GPU SNoC bus clock547 - description: GPU AHB clock548 549 # Disallow clocks for all other platforms with specific compatibles550 - if:551 properties:552 compatible:553 contains:554 enum:555 - cavium,smmu-v2556 - marvell,ap806-smmu-500557 - nvidia,smmu-500558 - qcom,qcs8300-smmu-500559 - qcom,qdu1000-smmu-500560 - qcom,sa8255p-smmu-500561 - qcom,sc7180-smmu-500562 - qcom,sdm670-smmu-500563 - qcom,sdm845-smmu-500564 - qcom,sdx55-smmu-500565 - qcom,sdx65-smmu-500566 - qcom,sm6350-smmu-500567 - qcom,sm6375-smmu-500568 then:569 properties:570 clock-names: false571 clocks: false572 573 - if:574 properties:575 compatible:576 contains:577 const: qcom,sm6375-smmu-500578 then:579 properties:580 power-domains:581 items:582 - description: SNoC MMU TBU RT GDSC583 - description: SNoC MMU TBU NRT GDSC584 - description: SNoC TURING MMU TBU0 GDSC585 586 required:587 - power-domains588 else:589 properties:590 power-domains:591 maxItems: 1592 593examples:594 - |+595 /* SMMU with stream matching or stream indexing */596 smmu1: iommu@ba5e0000 {597 compatible = "arm,smmu-v1";598 reg = <0xba5e0000 0x10000>;599 #global-interrupts = <2>;600 interrupts = <0 32 4>,601 <0 33 4>,602 <0 34 4>, /* This is the first context interrupt */603 <0 35 4>,604 <0 36 4>,605 <0 37 4>;606 #iommu-cells = <1>;607 };608 609 /* device with two stream IDs, 0 and 7 */610 master1 {611 iommus = <&smmu1 0>,612 <&smmu1 7>;613 };614 615 616 /* SMMU with stream matching */617 smmu2: iommu@ba5f0000 {618 compatible = "arm,smmu-v1";619 reg = <0xba5f0000 0x10000>;620 #global-interrupts = <2>;621 interrupts = <0 38 4>,622 <0 39 4>,623 <0 40 4>, /* This is the first context interrupt */624 <0 41 4>,625 <0 42 4>,626 <0 43 4>;627 #iommu-cells = <2>;628 };629 630 /* device with stream IDs 0 and 7 */631 master2 {632 iommus = <&smmu2 0 0>,633 <&smmu2 7 0>;634 };635 636 /* device with stream IDs 1, 17, 33 and 49 */637 master3 {638 iommus = <&smmu2 1 0x30>;639 };640 641 642 /* ARM MMU-500 with 10-bit stream ID input configuration */643 smmu3: iommu@ba600000 {644 compatible = "arm,mmu-500", "arm,smmu-v2";645 reg = <0xba600000 0x10000>;646 #global-interrupts = <2>;647 interrupts = <0 44 4>,648 <0 45 4>,649 <0 46 4>, /* This is the first context interrupt */650 <0 47 4>,651 <0 48 4>,652 <0 49 4>;653 #iommu-cells = <1>;654 /* always ignore appended 5-bit TBU number */655 stream-match-mask = <0x7c00>;656 };657 658 bus {659 /* bus whose child devices emit one unique 10-bit stream660 ID each, but may master through multiple SMMU TBUs */661 iommu-map = <0 &smmu3 0 0x400>;662 663 664 };665 666 - |+667 /* Qcom's arm,smmu-v2 implementation */668 #include <dt-bindings/interrupt-controller/arm-gic.h>669 #include <dt-bindings/interrupt-controller/irq.h>670 smmu4: iommu@d00000 {671 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";672 reg = <0xd00000 0x10000>;673 674 #global-interrupts = <1>;675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;678 #iommu-cells = <1>;679 power-domains = <&mmcc 0>;680 681 clocks = <&mmcc 123>,682 <&mmcc 124>;683 clock-names = "bus", "iface";684 };685