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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4 5$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Qualcomm APQ8064 IOMMU9 10maintainers:11 - David Heidelberg <david@ixit.cz>12 13description:14 The MSM IOMMU is an implementation compatible with the ARM VMSA short15 descriptor page tables. It provides address translation for bus masters16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.17 18properties:19 compatible:20 const: qcom,apq8064-iommu21 22 clocks:23 items:24 - description: interface clock for register accesses25 - description: functional clock for bus accesses26 27 clock-names:28 items:29 - const: smmu_pclk30 - const: iommu_clk31 32 reg:33 maxItems: 134 35 interrupts:36 description: Specifiers for the MMU fault interrupts.37 minItems: 138 items:39 - description: non-secure mode interrupt40 - description: secure mode interrupt (for instances which supports it)41 42 "#iommu-cells":43 const: 144 description: Each IOMMU specifier describes a single Stream ID.45 46 qcom,ncb:47 $ref: /schemas/types.yaml#/definitions/uint3248 description: The total number of context banks in the IOMMU.49 minimum: 150 maximum: 451 52required:53 - reg54 - interrupts55 - clocks56 - clock-names57 - qcom,ncb58 59additionalProperties: false60 61examples:62 - |63 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>64 #include <dt-bindings/interrupt-controller/irq.h>65 #include <dt-bindings/interrupt-controller/arm-gic.h>66 67 iommu@7500000 {68 compatible = "qcom,apq8064-iommu";69 reg = <0x07500000 0x100000>;70 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,71 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;72 clocks = <&clk SMMU_AHB_CLK>,73 <&clk MDP_AXI_CLK>;74 clock-names = "smmu_pclk",75 "iommu_clk";76 #iommu-cells = <1>;77 qcom,ncb = <2>;78 };79