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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies legacy IOMMU implementations8 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description: |13 Qualcomm "B" family devices which are not compatible with arm-smmu have14 a similar looking IOMMU, but without access to the global register space15 and optionally requiring additional configuration to route context IRQs16 to non-secure vs secure interrupt line.17 18properties:19 compatible:20 oneOf:21 - items:22 - enum:23 - qcom,msm8916-iommu24 - qcom,msm8953-iommu25 - const: qcom,msm-iommu-v126 - items:27 - enum:28 - qcom,msm8953-iommu29 - qcom,msm8976-iommu30 - const: qcom,msm-iommu-v231 32 clocks:33 items:34 - description: Clock required for IOMMU register group access35 - description: Clock required for underlying bus access36 37 clock-names:38 items:39 - const: iface40 - const: bus41 42 power-domains:43 maxItems: 144 45 reg:46 maxItems: 147 48 ranges: true49 50 qcom,iommu-secure-id:51 $ref: /schemas/types.yaml#/definitions/uint3252 description:53 The SCM secure ID of the IOMMU instance.54 55 '#address-cells':56 const: 157 58 '#size-cells':59 const: 160 61 '#iommu-cells':62 const: 163 64patternProperties:65 "^iommu-ctx@[0-9a-f]+$":66 type: object67 additionalProperties: false68 properties:69 compatible:70 enum:71 - qcom,msm-iommu-v1-ns72 - qcom,msm-iommu-v1-sec73 - qcom,msm-iommu-v2-ns74 - qcom,msm-iommu-v2-sec75 76 interrupts:77 maxItems: 178 79 reg:80 maxItems: 181 82 qcom,ctx-asid:83 $ref: /schemas/types.yaml#/definitions/uint3284 description:85 The ASID number associated to the context bank.86 87 required:88 - compatible89 - interrupts90 - reg91 92required:93 - compatible94 - clocks95 - clock-names96 - ranges97 - '#address-cells'98 - '#size-cells'99 - '#iommu-cells'100 101additionalProperties: false102 103examples:104 - |105 #include <dt-bindings/clock/qcom,gcc-msm8916.h>106 #include <dt-bindings/interrupt-controller/arm-gic.h>107 108 apps_iommu: iommu@1e20000 {109 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";110 reg = <0x01ef0000 0x3000>;111 clocks = <&gcc GCC_SMMU_CFG_CLK>,112 <&gcc GCC_APSS_TCU_CLK>;113 clock-names = "iface", "bus";114 qcom,iommu-secure-id = <17>;115 #address-cells = <1>;116 #size-cells = <1>;117 #iommu-cells = <1>;118 ranges = <0 0x01e20000 0x40000>;119 120 /* mdp_0: */121 iommu-ctx@4000 {122 compatible = "qcom,msm-iommu-v1-ns";123 reg = <0x4000 0x1000>;124 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;125 };126 };127