89 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip IOMMU8 9maintainers:10 - Heiko Stuebner <heiko@sntech.de>11 12description: |+13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for14 its master device. Each slave device is bound to a single master device and15 shares its clocks, power domain and irq.16 17 For information on assigning IOMMU controller to its peripheral devices,18 see generic IOMMU bindings.19 20properties:21 compatible:22 oneOf:23 - enum:24 - rockchip,iommu25 - rockchip,rk3568-iommu26 - items:27 - enum:28 - rockchip,rk3588-iommu29 - const: rockchip,rk3568-iommu30 31 reg:32 items:33 - description: configuration registers for MMU instance 034 - description: configuration registers for MMU instance 135 minItems: 136 37 interrupts:38 items:39 - description: interruption for MMU instance 040 - description: interruption for MMU instance 141 minItems: 142 43 clocks:44 items:45 - description: Core clock46 - description: Interface clock47 48 clock-names:49 items:50 - const: aclk51 - const: iface52 53 "#iommu-cells":54 const: 055 56 power-domains:57 maxItems: 158 59 rockchip,disable-mmu-reset:60 $ref: /schemas/types.yaml#/definitions/flag61 description: |62 Do not use the mmu reset operation.63 Some mmu instances may produce unexpected results64 when the reset operation is used.65 66required:67 - compatible68 - reg69 - interrupts70 - clocks71 - clock-names72 - "#iommu-cells"73 74additionalProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/rk3399-cru.h>79 #include <dt-bindings/interrupt-controller/arm-gic.h>80 81 vopl_mmu: iommu@ff940300 {82 compatible = "rockchip,iommu";83 reg = <0xff940300 0x100>;84 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;85 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;86 clock-names = "aclk", "iface";87 #iommu-cells = <0>;88 };89