193 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX Messaging Unit (MU)8 9maintainers:10 - Dong Aisheng <aisheng.dong@nxp.com>11 12description: |13 The Messaging Unit module enables two processors within the SoC to14 communicate and coordinate by passing messages (e.g. data, status15 and control) through the MU interface. The MU also provides the ability16 for one processor to signal the other processor using interrupts.17 18 Because the MU manages the messaging between processors, the MU uses19 different clocks (from each side of the different peripheral buses).20 Therefore, the MU must synchronize the accesses from one side to the21 other. The MU accomplishes synchronization using two sets of matching22 registers (Processor A-facing, Processor B-facing).23 24properties:25 compatible:26 oneOf:27 - const: fsl,imx6sx-mu28 - const: fsl,imx7ulp-mu29 - const: fsl,imx8ulp-mu30 - const: fsl,imx8-mu-scu31 - const: fsl,imx8-mu-seco32 - const: fsl,imx8ulp-mu-s433 - const: fsl,imx93-mu-s434 - const: fsl,imx95-mu35 - const: fsl,imx95-mu-ele36 - const: fsl,imx95-mu-v2x37 - items:38 - const: fsl,imx93-mu39 - const: fsl,imx8ulp-mu40 - items:41 - enum:42 - fsl,imx7s-mu43 - fsl,imx8mq-mu44 - fsl,imx8mm-mu45 - fsl,imx8mn-mu46 - fsl,imx8mp-mu47 - fsl,imx8qm-mu48 - fsl,imx8qxp-mu49 - const: fsl,imx6sx-mu50 - description: To communicate with i.MX8 SCU with fast IPC51 items:52 - const: fsl,imx8-mu-scu53 - enum:54 - fsl,imx8qm-mu55 - fsl,imx8qxp-mu56 - const: fsl,imx6sx-mu57 58 reg:59 maxItems: 160 61 interrupts:62 minItems: 163 maxItems: 264 65 interrupt-names:66 minItems: 167 items:68 - const: tx69 - const: rx70 71 "#mbox-cells":72 description: |73 <&phandle type channel>74 phandle : Label name of controller75 type : Channel type76 channel : Channel number77 78 This MU support 6 type of unidirectional channels, each type79 has 4 channels except RST channel which only has 1 channel.80 A total of 21 channels. Following types are81 supported:82 0 - TX channel with 32bit transmit register and IRQ transmit83 acknowledgment support.84 1 - RX channel with 32bit receive register and IRQ support85 2 - TX doorbell channel. Without own register and no ACK support.86 3 - RX doorbell channel.87 4 - RST channel88 5 - Tx doorbell channel. With S/W ACK from the other side.89 const: 290 91 clocks:92 maxItems: 193 94 fsl,mu-side-b:95 description: boolean, if present, means it is for side B MU.96 type: boolean97 98 power-domains:99 maxItems: 1100 101 ranges: true102 103 '#address-cells':104 const: 1105 106 '#size-cells':107 const: 1108 109patternProperties:110 "^sram@[a-f0-9]+":111 $ref: /schemas/sram/sram.yaml#112 unevaluatedProperties: false113 114required:115 - compatible116 - reg117 - interrupts118 - "#mbox-cells"119 120allOf:121 - if:122 properties:123 compatible:124 enum:125 - fsl,imx93-mu-s4126 then:127 properties:128 interrupt-names:129 minItems: 2130 interrupts:131 minItems: 2132 133 else:134 properties:135 interrupts:136 maxItems: 1137 not:138 required:139 - interrupt-names140 141 - if:142 not:143 properties:144 compatible:145 const: fsl,imx95-mu146 then:147 patternProperties:148 "^sram@[a-f0-9]+": false149 150additionalProperties: false151 152examples:153 - |154 #include <dt-bindings/interrupt-controller/arm-gic.h>155 156 mailbox@5d1b0000 {157 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";158 reg = <0x5d1b0000 0x10000>;159 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;160 #mbox-cells = <2>;161 };162 163 - |164 #include <dt-bindings/interrupt-controller/arm-gic.h>165 166 mailbox@445b0000 {167 compatible = "fsl,imx95-mu";168 reg = <0x445b0000 0x10000>;169 ranges;170 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;171 #address-cells = <1>;172 #size-cells = <1>;173 #mbox-cells = <2>;174 175 sram@445b1000 {176 compatible = "mmio-sram";177 reg = <0x445b1000 0x400>;178 ranges = <0x0 0x445b1000 0x400>;179 #address-cells = <1>;180 #size-cells = <1>;181 182 scmi-sram-section@0 {183 compatible = "arm,scmi-shmem";184 reg = <0x0 0x80>;185 };186 187 scmi-sram-section@80 {188 compatible = "arm,scmi-shmem";189 reg = <0x80 0x80>;190 };191 };192 };193